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2.1i 4KX* Map - ERROR : DesignRules: 207 - Blockcheck: The pin "O" on comp (mapped physical logic cell) "inst_name" is configured to be used but has no signal attached to it.
Record #7868
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Product Version: 2.1i
Problem Title:
2.1i 4KX* Map - ERROR : DesignRules: 207 - Blockcheck: The pin "O" on comp (mapped physical
logic cell) "inst_name" is configured to be used but has no signal attached to it.
Problem Description:
URGENCY: standard
GENERAL DESCRIPTION:
ERROR : DesignRules: 207 - Blockcheck: The pin "O" on comp (mapped
physical logic cell) "inst_name" is configured to be used but has no signal
attached to it. The above error also occurs as a warning in map.
Solution 1:
This has been seen to occur if the obuft has it's input connected to GND
in the design. MAP is optimising out the GND but is not replacing it with
the GND internal to the IOB It is however keeping the obuft and the signal
from the O pin of the IOB to the input of the obuft, hence leaving the O pin
of the IOB unconnected.
As a workaround you can place a KEEP on the signal between the GND
and the obuft. This is not optimal.
Solution 2:
This problem is fixed in the latest 2.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates/
End of Record #7868 - Last Modified: 12/13/99 13:25 |
