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EXEMPLAR:How to infer Virtex Block RAM in HDL? (Verilog/VHDL)
Record #7929
Product Family: Software
Product Line: Exemplar
Product Part: Exemplar
Problem Title:
EXEMPLAR:How to infer Virtex Block RAM in HDL? (Verilog/VHDL)
Problem Description:
Urgency: standard
General Description:
LeonardoSpectrum can map your memory statements in Verilog or VHDL to the block
RAMs on all Virtex devices. The following is a list of the details for block RAMs in
LeonardoSpectrum.
- Virtex Block RAMs are completely synchronous - both read and write operations
are synchronous.
- LeonardoSpectrum infers single port RAMs - RAMs with both read and write on
the same address - and, dual port RAMs - RAMs with separate read and write
addresses. Currently, LeonardoSpectrum does not infer dual port RAMs that read
both read and write address.
- Virtex Block RAMs support RST (reset) and ENA (enable) pins. Currently,
LeonardoSpectrum does not infer RAMs which use the functionality of the RST
and ENA pins.
Variables:
Set the following variable to false if you do not want RAM extraction. Default is
true.
set extract_ram false
set extract_ram true (default)
By default, RAMs that are mappable to block RAMs, are mapped to block RAMs. You
can disable mapping to block RAMs by setting the attribute block_ram to false.
set_attribute -name block_ram -value false
In this case, the RAM is implemented using select RAMs if possible.
Please Note: The variant of single port RAM that is implemented using block RAMs,
cannot be implemented using select RAMs.
Solution 1:
// Verilog Example:
// Tested in Leonardo Spectrum 1999.1f
module ram(din, we, addr, clk, dout);
parameter data_width=7, address_width=6,mem_elements=64;
input [data_width-1:0] din;
input [address_width-1:0] addr;
input we, clk;
output [data_width-1:0] dout;
reg [data_width-1:0] mem[mem_elements-1:0];
// Exemplar attribute mem block_ram FALSE. This comment sets the block_ram
attribute to FALSE on the signal mem.The block_ram attribute must be set on the memory
signal.
reg [address_width - 1:0] addr_reg;
always @(posedge clk)
begin
addr_reg <= addr;
if (we)
mem[addr] <= din;
end
assign dout = mem[addr_reg];
endmodule
Solution 2:
-- VHDL Example of Block RAMs
-- tested in Leonardo Spectrum 1999.1f
library ieee, exemplar;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram_example1 is
generic(data_width: integer:= 8;
address_width:integer := 8;
mem_depth: integer:= 256);
port (data: in std_logic_vector(data_width-1 downto 0);
address: in unsigned(address_width-1 downto 0);
we, clk: in std_logic;
q: out std_logic_vector(data_width-1 downto 0));
end ram_example1;
architecture ex1 of ram_example1 is
type mem_type is array (mem_depth-1 downto 0) of
std_logic_vector (data_width-1 downto 0);
signal mem: mem_type;
signal raddress : unsigned(address_width-1 downto 0);
begin
l0: process (clk, we, address)
begin
if (clk = '1' and clk'event) then
raddress <= address;
if (we = '1') then
mem(to_integer(raddress)) <= data;
end if;
end if;
end process;
l1: process (clk, address)
begin
if (clk = '1' and clk'event) then
q <= mem(to_integer(address));
end if;
end process;
end ex1;
End of Record #7929 - Last Modified: 11/05/99 18:32 |
