Xilinx Answer #7947 : EXEMPLAR: How to instantiate and initialize Virtex Select BlockRAM?

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EXEMPLAR: How to instantiate and initialize Virtex Select BlockRAM?

Record #7947
Product Family: Software

Product Line: Exemplar

Product Part: Exemplar

Problem Title:
EXEMPLAR: How to instantiate and initialize Virtex Select BlockRAM?

Problem Description:
Urgency: Standard

General Description:
How to instantiate and initialize Virtex Select BlockRAM+
using EXEMPLAR Leonardo Spectrum?

You can instantiate RAMB* cell as blackbox.
The INIT_** attribute can be passed as string in HDL file as well as the script file. The HDL code below shows how to pass INIT in the VHDL file.
Alternatively, you can also do the following in exemplar command script:
set_attribute -instance "inst_ramb4_s4" -name INIT_00 -type string
-value "1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100"

Note: Tested with Spectrum 1999.1e

Solution 1:

-- VHDL example

library IEEE;
use IEEE.std_logic_1164.all;

entity spblkrams is port(CLK : in std_logic; EN : in std_logic; RST : in std_logic; WE : in std_logic; ADDR : in std_logic_vector(11 downto 0); DI : in std_logic_vector(15 downto 0); DORAMB4_S4 : out std_logic_vector(3 downto 0); DORAMB4_S8 : out std_logic_vector(7 downto 0)); end;

architecture struct of spblkrams is

component RAMB4_S4 port (DI : in STD_LOGIC_VECTOR (3 downto 0); EN : in STD_ULOGIC; WE : in STD_ULOGIC; RST : in STD_ULOGIC; CLK : in STD_ULOGIC; ADDR : in STD_LOGIC_VECTOR (9 downto 0); DO : out STD_LOGIC_VECTOR (3 downto 0)); end component;

component RAMB4_S8 port (DI : in STD_LOGIC_VECTOR (7 downto 0); EN : in STD_ULOGIC; WE : in STD_ULOGIC; RST : in STD_ULOGIC; CLK : in STD_ULOGIC; ADDR : in STD_LOGIC_VECTOR (8 downto 0); DO : out STD_LOGIC_VECTOR (7 downto 0));
end component;

attribute INIT_00: string;
attribute INIT_00 of INST_RAMB4_S4: label is
"1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100";
attribute INIT_00 of INST_RAMB4_S8: label is
"1F1E1D1C1B1A191817161514131211100F
0E0D0C0B0A09080706050403020100";

begin

INST_RAMB4_S4 : RAMB4_S4 port map (
                DI => DI(3 downto 0),
                EN => EN,
                WE => WE,
                RST => RST,
                CLK => CLK,
                ADDR => ADDR(9 downto 0),
                DO => DORAMB4_S4
                );

INST_RAMB4_S8 : RAMB4_S8 port map (
                DI => DI(7 downto 0),
                EN => EN,
                WE => WE,
                RST => RST,
                CLK => CLK,
                ADDR => ADDR(8 downto 0),
                DO => DORAMB4_S8
                );

end struct;

Solution 2:

//Verilog Example

module block_ram_ex (CLK, WE, ADDR, DIN, DOUT);
input CLK, WE;
input [8:0] ADDR;
input [7:0] DIN;
output [7:0] DOUT;

RAMB4_S8 U0 (.WE(WE), .EN(1'b1), .RST(1'b0), .CLK(CLK),
    .ADDR(ADDR), .DI(DIN), .DO(DOUT));
//exemplar attribute U0 INIT_00
1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100
endmodule

End of Record #7947 - Last Modified: 10/27/99 15:09

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