Answers Database
2.1i 9500/xl Tsim- Timing model incorrect for negative edge triggered global clock signals
Record #7948
Product Family: Software
Product Line: CPLD Implementation
Product Part: tsim
Product Version: 2.1is4
Problem Title:
2.1i 9500/xl Tsim- Timing model incorrect for negative edge triggered global clock signals
Problem Description:
Urgency: Standard
General Description:
There is an error in the timing model such that the timing for
a negative edge triggered flip flop on the global clock net
uses the timing for a product-term clock net - thus appearing
slower than it really operates. This problem is not seen for
positive edge triggered registers.
Solution 1:
This is fixed in the latest 2.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates/
End of Record #7948 - Last Modified: 02/02/00 10:54 | 
