Answers Database
FPGA Express 3.3: FPGA-buffermap-25 occurs when clock signal is connected to non-clock loads
Record #7949
Problem Title:
FPGA Express 3.3: FPGA-buffermap-25 occurs when clock signal is connected to non-clock loads
Problem Description:
Urgency: Standard
General Description:
FPGA Express 3.3 may report the following error:
Error: Buffer allocation detected possible drivers on the same net as clock input
'/virtex_clk-Optimized/clk'. (FPGA-buffermap-25)
This error may occur when a clock signal sources inferred flip flops and other non-clock
loads (combinatorial logic and/or black boxes). This been seen when FPGA Express
infers a clock buffer on this signal or when the user specifies a clock buffer via the
Express Constraints editor.
Solution 1:
In any case, the workaround is to instantiate the clock buffer in your HDL code.
End of Record #7949 - Last Modified: 11/10/99 16:38 |
