Answers Database
2.1i Map - Pack errors on floorplanned gates do not always report problem area.
Record #7965
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Product Version: 2.1i
Problem Title:
2.1i Map - Pack errors on floorplanned gates do not always report problem area.
Problem Description:
Urgency: Standard
General Description:
If logic constrained to a an F/G LUT is not packable, and the logic consists of
only gates (no FMAP) then map fails to report the problem area and user has no
clue as to where the problem is.
ERROR:OldMap:532 - Unable to obey design constraints which require the
combination of the following symbols into a single CLB:
There are more than two combinational outputs required. These symbols share
the same LOC parameter.
Solution 1:
A brute force technique for identifying the problem area is available:
1. Re-sort the floorplan (.mfp) so that all FG constraints are at the
beginning of the file.
2. Make a backup copy of the sorted .mfp file
3. Remove half of the FG constraints and re-run map
4. Success or failure identifies the section of the .mfp file with the
problem constraint.
5. Restore the sorted .mfp file from the backup.
5. Continue the binary search, where each iteration cuts the known
problem area in half until the problem constraint is identified.
Example of .mfp file with 800 FG constraints:
Test Result Known problem area
Remove lines 1-400 Fail 401-800
Remove lines 401-600 Pass 401-600
Remove lines 401-500 Fail 501-600
Remove lines 501-550 Fail 551-600
Remove lines 551-575 Pass 551-575
Remove lines 551-563 Fail 564-575
Remove lines 564-569 Fail 570-575
Remove lines 570-572 Pass 570-572
Remove lines 570-571 Pass 570-571
Remove line 570 Fail 571
Remove line 571 Pass 571 verified
End of Record #7965 - Last Modified: 10/28/99 10:36 | 
