Answers Database
2.1i COREGEN, MTI: "WARNING[1]:No default binding for component" messages when compiling VHDL designs containing Coregen modules
Record #7973
Product Family: Software
Product Line: LogiCore
Product Part: Coregen IP Modules
Problem Title:
2.1i COREGEN, MTI: "WARNING[1]:No default binding for component" messages when compiling
VHDL designs containing Coregen modules
Problem Description:
Urgency: standard
General Description:
"WARNING[1]:No default binding for component" messages are seen
when compiling VHDL behavioral simulation netlists containing CORE Generator
modules in ModelSIM.
Example:
# WARNING[1]: vfft64_lab.vhd(168): No default binding for component: "ram6416".
(No entity named "ram6416" was found)
Solution 1:
In most cases, these warnings are not a cause for concern when they are
associated with Coregen modules if the modules have been instantiated properly.
There will be warnings similar to this for all 2.1i Coregen modules because the
simulator encounters the component declaration for the Coregen module without
first seeing an entity declaration for it. The binding problem is later resolved lower down
in the design code in the VHDL configuration block, which points to the simulation
model in the compiled "xilinxcorelib" library that is used to model the core.
You should verify that the reference to the core in the configuration block has been
merged successfully into the design simulation by monitoring the compile messages that
follows this warning.
For example, say we have instantiated a dual port block memory module in a
design called "vfft64_lab", and the reference to the block memory module is
specified in a VHDL configuration block called cfg_vfft64_lab_tb in the testbench file,
vfft64_lab_tb.vhd.
If the module binding has been resolved successfully, you should see something like this:
# -- Compiling configuration cfg_vfft64_lab_tb
# -- Loading entity vfft64_lab_tb
# -- Loading architecture testbench of vfft64_lab_tb
# -- Loading architecture xilinx of fft64
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Loading entity vfft64
# -- Loading package ul_utils
# -- Loading package mem_init_file_pack
# -- Loading entity c_mem_dp_block_v1_0
The lines of interest are:
1. the line indicating that the configuration is being compiled:
# -- Compiling configuration cfg_vfft64_lab_tb
2. The line indicating that the entity for the module you instantiated (c_mem_dp_block_v1_0
for this dual port block memory example), as well as the modules it depends on are being loaded:
# -- Loading package ul_utils
# -- Loading package mem_init_file_pack
# -- Loading entity c_mem_dp_block_v1_0
As long as you can verify that the necessary packages and entities required by the module have been
loaded, the warning about "no default binding" for this component at the beginning can be ignored.
End of Record #7973 - Last Modified: 11/02/99 11:20 |
