Answers Database
VirtexE CLKDLL: How to create 4X clock using VirtexE CLKDLLs
Record #8005
Product Family: Hardware
Product Line: Virtex
Product Part: Virtex General Hardware
Problem Title:
VirtexE CLKDLL: How to create 4X clock using VirtexE CLKDLLs
Problem Description:
Urgency: Standard
Problem Description:
How to create 4X clocks using VirtexE CLKDLLs
Solution 1:
VirtexE has more CLKDLLs than Virtex has. There are total of 8, 4 primary CLKDLLs,
and 4 secondary CLKDLLs. The secondary CLKDLL has a dedicated feedback loop
from the 2X output to the FB pin. Therefore, generating a 4X clock only needs to use
1 BUFG instead of using 2 as in creating 4X clocks in Virtex devices.
For more information on CLKDLL, please see xapp132 at
http://www.xilinx.com/xapp/xapp132.pdf
The following is an example VHDL code of how to create a 4X clock in VirtexE:
library ieee;
use ieee.std_logic_1164.all;
entity useclk is
port ( clock, reset, din : in std_logic;
locked, dout: out std_logic);
end useclk;
architecture useclk_arch of useclk is
component BUFG port (I: in std_logic; O: out std_logic);
end component;
component IBUFG port (I: in std_logic; O: out std_logic);
end component;
component SRL16 port (A0, A1, A2, A3, CLK, D : in std_logic; Q : out std_logic);
end component;
component CLKDLL
port (
CLKIN, CLKFB, RST : in std_logic;
CLK0, CLK90, CLK180, CLK270, CLK2X, CLKDV, LOCKED : out std_logic);
end component;
signal clk_int, clk, clk_2x, clk_2x_bufg, clk_4x, clk_4x_bufg : std_logic;
signal lock1st, lock1st_out, b, c, d, e, f, g, h, i, gd: std_logic;
begin
gd<='0';
J1 : IBUFG port map (I=>clock, O=>clk);
U1 : CLKDLL
port map(
CLKIN=>clk,
RST=>gd,
CLKFB=>clk_2x,
CLK0=>clk_int,
CLK90=>b,
CLK180=>c,
CLK270=>d,
CLKDV=>e,
CLK2X=>clk_2x,
LOCKED=>lock1st);
U2 : SRL16 port map(
A0=>gd,
A1=>gd,
A2=>gd,
A3=>gd,
CLK=>clk_2x,
D=>lock1st,
Q=>lock1st_out);
U3 : CLKDLL port map(
CLKIN=>clk_2x,
RST=>not lock1st_out,
CLKFB=>clk_4x_bufg,
CLK0=>clk_int,
CLK90=>f,
CLK180=>g,
CLK270=>h,
CLKDV=>i,
CLK2X=>clk_4x,
LOCKED=>locked);
U0 : BUFG port map (I=>clk_4x, O=>clk_4x_bufg);
process (clk_4x_bufg, reset)
begin
if (reset='1') then
dout<='0';
elsif (clk_4x_bufg'event and clk_4x_bufg='1') then
dout<=din;
end if;
end process;
end useclk_arch;
End of Record #8005 - Last Modified: 11/08/99 14:16 |
