Answers Database


VirtexE CLKDLL: What are the input clock frequency range for VirtexE CLKDLLs to be locked.


Record #8006

Product Family: Hardware

Product Line: Virtex

Product Part: Virtex General Hardware

Problem Title:
VirtexE CLKDLL: What are the input clock frequency range for VirtexE CLKDLLs to be locked.


Problem Description:
Urgency: Standard

Problem Description:

What are the input clock frequency range for VirtexE CLKDLLs to be locked.


Solution 1:

For -6 parts:

		     Min(Mhz)	  Max(Mhz)
CLKDLL:       25		130
CLKDLLHF:   60		     260

For -7 parts:

		     Min(Mhz)	  Max(Mhz)
CLKDLL:       25		160
CLKDLLHF:   60		     320




End of Record #8006 - Last Modified: 11/04/99 13:42

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!