Answers Database
Virtex CLKDLL: Why is it the output jitter spec on the data book is less than the cycle-to-cycle input jitter
Record #8007
Product Family: Hardware
Product Line: Virtex
Product Part: Virtex General Hardware
Problem Title:
Virtex CLKDLL: Why is it the output jitter spec on the data book is less than the
cycle-to-cycle input jitter
Problem Description:
Urgency: Standard
Problem Description:
The data book indicates that the cycle-to-cycle input jitter as +/-300ps, but the output
cycle-to-cycle jitter is +/-60ps. How is it possilbe that the output jitter is shorter than
the input jitter?
Solution 1:
The DLL output jitter and skew specs do not include input clock jitter.
Since input clock jitter can vary considerably between customer applications,
it doesn't make sense to try to include a value for that in the DLL output specs.
Thus, the DLL output jitter spec of +/-60ps is the amount of jitter that the DLL
can add to the existing input clock jitter. Remember that the DLL is a delay line, not
a clock generator (like a PLL), so a clean input clock will lead to a clean output clock,
and an ugly input clock will lead to an ugly output clock (with the exception that
we can duty-cycle correct the input clock). E.g., if the user's input clock has
+/-200ps of jitter, then the DLL output clock could have up to +/-260ps of jitter.
End of Record #8007 - Last Modified: 11/04/99 13:57 |
