Answers Database 2.1i COREGEN, SYNOPSYS VSS: How do I compile the Coregen Modules for VSS simulation? Record #8015 Product Family: Software Product Line: Coregen Product Part: Coregen Product Version: 2.1 Problem Title: 2.1i COREGEN, SYNOPSYS VSS: How do I compile the Coregen Modules for VSS simulation? Problem Description: Urgency: Standard General Description: How do I compile the CORE Generator library models for simulation in Synopsys VSS? Solution 1: 1. Read the Coregen User Guide documentation (accessible from Help-> Online Documentation       in the CORE Generator GUI) for instructions on extracting the models and setting up your       library directory. 2. You must declare a working directory called xilinxcorelib to which the CORE Generator models       will be compiled.       Example: xilinxcorelib : <path_to_directory>/xilinxcorelib 3. Your .synopsys_vss.setup needs to be in the same directory as where vhdlan is      being run. Your .synopsys_vss.setup must contain at least the following: TIMEBASE = NS TIME_RES_FACTOR = 0.01 WORK > DEFAULT DEFAULT : . xilinxcorelib : <path_to_directory>/xilinxcorelib -- VHDL library to UNIX dir mappings -- SYNOPSYS : $SYNOPSYS/packages/synopsys/lib IEEE : $SYNOPSYS/packages/IEEE/lib 4. Command line for compiling the models (see (Xilinx Solution #6250) for the compilation       order to be used for the latest IP release):       vhdlan -i -w xilinxcorelib <path_to_extracted_Coregen_libraries>/<filename>.vhd End of Record #8015 - Last Modified: 11/24/99 19:20

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