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2.1i VirtexE Map - Map does not make use of the fastdll feedback path between DLLIOBs and Secondary DLLs.
Record #8046
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Product Version: 2.1i
Problem Title:
2.1i VirtexE Map - Map does not make use of the fastdll feedback path between DLLIOBs and
Secondary DLLs.
Problem Description:
Urgency: Standard
General Description:
Map does not make use of the fastdll feedback path between DLLIOBs and Secondary DLLs. Instead, a
standard IOB is used with a path between the I pin of the IOB and the CLKFB pin of the DLL.
Solution 1:
This problem can be worked around by modifying the IOB configuration in
FPGA Editor:
1. Shift-Select net between IOB I pin and CLKFB pin of DLL, hit delete button to remove net.
2. Select and Attribute IOB, change configuration to DLLIOB, save.
3. Shift-Select IOB to open Logic Block Editor, enable input path to DLLFB pin, save.
4. Select DLLFB pin on DLLIOB, shift-select CLKFB pin on DLL, select Add button, save.
This problem will be fixed in the next major release (as yet unamed after 2.1i) which is currently
scheduled for March, 2000.
Solution 2:
This problem can also be worked around by using a hard macro (.nmc file)
to describe the DLLIOB connectivity. This work around involves an
initial investment of time, but does not have to be repeated for every
design iteration.
The following steps describe how to make a DLLIOB hard macro for use
with the off chip fast feedback DLL in the Virtex-E.
Please see XAPP 132 (http://support.xilinx.com/xapp/xapp132.pdf) for
more
information on using the DLL.
1. Open FPGA Editor
2. Make sure that you are in edit mode.
a. Go to the 'File' pull down menu.
b. Select 'Main Properties...'
c. Change the 'Edit Mode' from 'Read Only' to 'Read Write'.
d. Hit the 'OK' button.
3. Open a new project.
a. Go to the 'File' pull down menu.
b. Select 'New'.
c. Select the 'Macro' option.
d. Type in a file name.
e. Select a Virtex-E part.
f. Hit the 'OK' button.
4. Add a DLLIOB.
a. Select a 'DLLIOB'. This IOB will be a bonded IOB closest to a global
clock IOB.
b. Go to the 'Edit' pull down menu and select 'Add'.
c. Under 'Name' put in a description that you like.
d. Under 'Type' make sure that it is selected to 'DLLIOB'
e. Hit the 'OK' button.
5. Add the DLL feedback pin.
a. Highlite the right most pin of the set of three pins.
b. Go to the 'Edit' pull down menu and select 'Add Macro External Pin'.
c. Under 'External Name' type in the pin name.
d. Make sure the the 'Type of Pin' is set to 'OUTPUT'.
e. Hit the 'OK' button.
6. That is it. Save your new macro.
Below is an example of how to instantiate this new macro in VHDL:
-- component declaration
component dll_feed_back -- file name of my hard macro
port (FEEDBACKPIN : out std_logic); -- my external pin name (port)
end component;
-- component instantiation
dll_feed_back_inst : dll_feed_back port map (FEEDBACKPIN =>
dll_signal_name);
Below is an example of how to isntantiate this new macro in Verilog:
// module instantiation
// module name (hard macro file name) is dll_feed_back
// port name is FEEDBACKPIN
dll_feed_back dll_feed_back_inst (.FEEDBACKPIN(dll_signal_name)) ;
End of Record #8046 - Last Modified: 11/15/99 13:15 |
