Xilinx Answer #8065 : COREGEN: How to generate a VERILOG or VHDL post-NGDBUILD gate level simulation netlist from a standalone EDIF netlist

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COREGEN: How to generate a VERILOG or VHDL post-NGDBUILD gate level simulation netlist from a standalone EDIF netlist

Record #8065
Product Family: Software

Product Line: LogiCore

Product Part: Coregen IP Modules

Problem Title:
COREGEN: How to generate a VERILOG or VHDL post-NGDBUILD gate level simulation netlist from a standalone EDIF netlist

Problem Description:
Urgency: standard

General Description:
How to generate a VERILOG or VHDL post-NGDBUILD simulation netlist for an
EDIF netlist (for example, the EDIF implementation netlist for a CORE Generator module, or an EDIF netlist generated for a user-created design block)

Solution 1:

1. Generate an NGD file for the core:

ngdbuild -p <part_type> corename.edn ----> yields a file named corename.NGD

Example:

ngdbuild -p xcv300bg432-4 bram2048x8 ---> yields a file named bram2048x8.NGD

(If you are using the Xilinx Design Manager, this is equivalent to running only the Translate stage in the Flow Engine, targeting an XCV300bg432-4 part type.)

2. Then generate a gate level simulation netlist with the appropriate translator (NGD2VHDL for a VHDL netlist, and NGD2VER for a Verilog netlist). Note
that you must run this in command line mode, and you MUST include the .NGD
extension):

ngd2ver corename.NGD (Verilog) ngd2vhdl corename.NGD (VHDL)

3. If you are performing VHDL behavioral simulation and are substituting this new model for a CORE Generator module, you will only need a component and instantiation block for both simulation and synthesis. The configuration snippet from
the CORE Genrerator .VHO file should be commented out. For example, for an
8-bit adder, the following block would be commented out:

-- synopsys translate_on -- for all : myadder8 use entity XilinxCoreLib.C_ADDSUB_V1_0(behavioral) -- generic map( -- c_sinit_val => "0", -- c_a_type => 0, -- c_sync_enable => 0, -- c_has_ainit => 0, -- c_sync_priority => 1, . . . (remaining generics omitted) -- end for;

-- synopsys translate_on

End of Record #8065 - Last Modified: 01/31/00 10:10

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