Answers Database
2.1i Virtex Map - Apparently legal MUXF5 pack is rejected.
Record #8148
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Product Version: 2.1i
Problem Title:
2.1i Virtex Map - Apparently legal MUXF5 pack is rejected.
Problem Description:
A case has been seen where the following configuration failed to pack successfully:
Both LUTs feed the MUXF5. The FFX input is shared with the MUXF5 Select which
can use the BX input. FFY has an external input which can use BY. Only inputs are
LUT pins and BX, BY. Only outputs are XQ, YQ and F5. This should work but fails
with the following pack error:
ERROR:xvkpu - Unable to obey design constraints (MACRONAME = hset, RLOC =
R3C3.S1) which require the combination of the following symbols into a single slice:
FLOP symbol "R.R.3.C.C.1_A/LS1" (Output Signal = ls(11))
LUT symbol "R.R.3.C.C.1_A/S2_D" (Output Signal = R.R.3.C.C.1_A/s2_msg)
LUT symbol "R.R.3.C.C.1_A/S2_H" (Output Signal = R.R.3.C.C.1_A/s2_hdr)
MUXF5 symbol "R.R.3.C.C.1_A/S2_M" (Output Signal = ns(27))
FLOP symbol "R.R.3.C.C.1_A/SR2_3" (Output Signal = R.R.3.C.C.1_A/w2z)
Unable to pack the register R.R.3.C.C.1_A/SR2_3 because of connectivity
restrictions.
The problem is that the flop intended for FFX can not always put there if another
flop in the CLB has already been processed and put in that location. The 2.1i release
does not support BEL constraints, so this pack will not always work depending on the
order of processing for the flops.
The next release will support BEL constraints (BEL = FFX) but this pack will also work
without them.
Solution 1:
This problem is fixed in the latest 2.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates/
End of Record #8148 - Last Modified: 12/14/99 17:39 |
