Answers Database


2.1i Virtex PAR - Memory leak seen during timing analysis of V800 design.


Record #8150

Product Family: Software

Product Line: Merged Core

Product Part: Timing

Problem Title:

2.1i Virtex PAR - Memory leak seen during timing analysis of V800 design.


Problem Description:
Urgency: Standard

General Description:
A case has been seen where PAR runs out of memory during initial timing analysis. Memory usage gradually increases until failure. Reproduced on a 1G NT machine.


Solution 1:

This problem is scheduled to be fixed in the next (as yet unnamed)
release following version 2.1i. This release is currently scheduled
for March, 2000.




End of Record #8150 - Last Modified: 12/15/99 09:55

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!