Answers Database
FPGA Configuration : [XC3000, XC4000, XC5200, Spartan] Data frame error information
Record #8158
Product Family: Web
Product Line: support.xilinx.com
Product Part: Configuration Problem Solver
Product Version: 1.0
Problem Title:
FPGA Configuration : [XC3000, XC4000, XC5200, Spartan] Data frame error information
Problem Description:
Urgency: Standard
General Description:
During configuration the FPGA checks each data frame for
the appropriate start and stop bits and by default performs a
Cyclic Redundancy Check (CRC) to ensure the transmitted
data was received correctly. If any of these bits cause a
mismatch then the configuration process is aborted and INIT
is driven low to signal the error. The following are some
possibilities why this may have occurred.
Solution 1:
Bitstream Targeted for Wrong Device:
The same FPGA device size may be available in multiple family
types and would thus have different bitstreams per family. For
example, the XC4010D, XC4010A, XC4010E, and XC4010XL
all have different data frame sizes and are therefore not bitstream
compatible.
Make sure that your design implementation targets the exact
same device as that on your application board.
Solution 2:
Timing violations and clock glitches:
Typically when connecting an FPGA directly to a memory
element performance characteristics and timing specifications
are not a point of concern. However, if the address or data paths
are being passed through secondary devices or are subject to
any extra delay, then the access time of the storage element
becomes important relative to the required setup time for the
FPGA. Verify that the timing characteristics for the configuration
data path of the application conforms to the Configuration Switching
Characteristics and Timing Specifications outlined in the Xilinx
Programmable Logic Data Book.
Signal glitching may be caused by interference from other signals
traced close by or by "Ground Bounce" from other devices. Make
sure that the FPGA is well decoupled. Xilinx recommends a 0.1uF
and 0.01uF capacitor pair per VCC/GND pair. Try to place these
as close to the FPGA as possible. More than an inch distance would
make them useless.
Verify that the Setup and Hold timing for the data to the clock
meet the specifications in the Data Book. Another problem
could be glitching on the clock line. Try adding a decoupling
capacitor to the clock line to filter out high frequency noise. A
50 pF cap should be sufficient. If the glitching is in the very high
frequency range then the capacitance of an oscilloscope probe
could actually be enough to mask it. Try restarting the configuration
while probing the CCLK line.
Solution 3:
Data shifted backwards:
Check to see if the data is backwards by capturing the first two
bytes of the Header on the DOUT pin. If the configuration data
is being accessed in byte words and shifted serially into the FPGA
then shifting in the wrong direction would result in observing
<0000 0100> instead of <0010 0000> on DOUT (not valid for Express
Mode configuration).
Solution 4:
Memory algorithm is outdated:
If the configuration data is stored in, and accessed from, a
memory device such as a Flash RAM, EPROM or SPROM
then check that the correct data is stored in the element.
Such programmable memory devices are constantly requiring
program algorithm updates. Programming a newer device
with an older algorithm can result in incorrect data being stored
even though the programmer may have verified the data.
Contact the manufacturer of the storage element or memory
device to obtain the correct algorithm version.
Solution 5:
If programming in Express Mode, and the
-g ExpressMode:Enable
is not set in BITGEN, a frame error can occur.
End of Record #8158 - Last Modified: 01/03/00 10:13 |
