Answers Database


Virtex-E LVDS: How to use LVDS IOSTANDARD in Virtex-E


Record #8187

Product Family: Software

Product Line: FPGA Implementation

Product Part: Virtex-E Pro-Unified Libs

Problem Title:
Virtex-E LVDS: How to use LVDS IOSTANDARD in Virtex-E


Problem Description:
Urgency: Standard

Problem Description:

How to design Virtex-E LVDS inputs and outputs


Solution 1:

When using LVDS iostandard, a ucf or a ncf file with complete pin loc information must be created to ensure that the IO banking rules are not violated. If a ucf or a ncf file is not used, PAR will issue errors. There are two ways to use LVDS iostandard:

1. Use IOSTANDARD attribute in the ucf file.
2. Instantiate LVDS input and output buffers.

LVDS Input buffer:

LVDS input buffer may be placed in wide number of IOB locations. The exact
location are dependent on the package that is used.
The Virtex-E package information lists the possible locations as IO_L#P for
the P-side and IO_L#N for the N-side where # is the pair number.

Using UCF file:

The following syntax can be used in the UCF file to set the IOSTANDARD to be LVDS:

NET <input net name> IOSTANDARD = LVDS;
NET <input net name> LOC=P(pin name);

Above is just an example for one LVDS input pin, in a real design, users must lock down all the IO pins in the ucf file. Otherwise, PAR will error out.

HDL Instantiation:

Only one input buffer is required to be instantiated in the design and placed
on the correct IO_L#P location. The N-side of the buffer
will be reserved and no other IOB will be allowed to be placed on this location.

In the physical device a configuration option is enabled that routes the pad
wire from the IO_L#N IOB to the differential input buffer located in the
IO_L#P IOB. The output of this buffer then drives the output of the IO_L#P
cell or the input register in the IO_L#P IOB. In FPGA_EDITOR it will appear
that the second buffer is unused. Any attempt to use this location for another
purpose will cause a DRC error from the software.

VHDL instantiation:
     data0_p : IBUF_LVDS port map (I=>data(0), O=>data_int(0));

Verilog instantiation:
      IBUF_LVDS data0_p (.I(data[0]), .O(data_int[0]));

Location constraints

All LVDS buffers must be explicitly placed on a device. For the input buffers
this may be done with the following constraint in the .ucf or .ncf file.

       NET data<0> LOC = D28; # IO_L0P



Solution 2:

Creating a LVDS Output Buffer

LVDS output buffer may be placed in wide number of IOB locations.
The exact location are dependent on the package that is used.
The Virtex-E package information lists the possible locations as IO_L#P
for the P-side and IO_L#N for the N-side where # is the pair number.

Using UCF file:


HDL Instantiation

Both output buffer are required to be instantiated in the design and
placed on the correct IO_L#P and IO_L#N locations. In addition, the
output (O) pins must be inverted with respect to each other.
(one HIGH and one LOW). Failure to follow these rules will lead to DRC
errors in software.

VHDL instantiation

      data0_p  : OBUF_LVDS port map (I=>data_int(0),   O=>data_p(0));
      data0_inv: INV	   port map (I=>data_int(0),   O=>data_n_int(0));
      data0_n  : OBUF_LVDS port map (I=>data_n_int(0), O=>data_n(0));

Verilog instantiation

      OBUF_LVDS data0_p   (.I(data_int[0]),   .O(data_p[0]));
      INV	data0_inv (.I(data_int[0],    .O(data_n_int[0]);
      OBUF_LVDS data0_n   (.I(data_n_int[0]), .O(data_n[0]));

Location constraints

All LVDS buffers must be explicitly placed on a device. For the output buffers
this may be done with the following constraint in the .ucf or .ncf file.

       NET data_p<0> LOC = D28; # IO_L0P
       NET data_n<0> LOC = B29; # IO_L0N



Solution 3:

Synchronous vs Asynchronous Outputs

If the outputs are synchronous (registered in the IOB) then any IO_L#P|N
pair pair may be used. If the output are asynchronous (no output register)
then they must use one of pairs that part of the same IOB group at the
end of a ROW or COLUMN in the device.

The LVDS pairs that may be used as asynchronous outputs are listed in
the Virtex-E pinout tables. Some pairs are marked as asynchronous capable
for all devices in that package and others are marked as only available for
that device in the package. If the device size may be changed at some
point in the product lifetime then only the common pairs for all packages
should be used.



Solution 4:

Adding an Output Register(synchronous output)

All LVDS buffers may have an output register in the IOB. The output
registers must be in both the P-side and N-side IOBs. All the
normal IOB register options are available (FD, FDE, FDC, FDCE,
FDP, FDPE, FDR, FDRE, FDS, FDSE, LD, LDE, LDC, LDCE,
LDP, LDPE). The register elements may be inferred or explicitly
instantiated in the HDL code.

Special care must be taken to insure that the D pins of the registers
are inverted and that the INIT states of the registers are opposite.
The clock pin (C), clock enable (CE) and set/reset (CLR/PRE or S/R)
pins must connect to the same source. Failure to do this will lead to a
DRC error in the software.

The register elements may be packed in the IOB using the IOB property
to TRUE on the register or by using the "map -pr [i|o|b]" where "i" is inputs
only, "o" is outputs only and "b" is both inputs and outputs.

Here is an example VHDL code of using LVDS registered outputs:

library ieee;
use ieee.std_logic_1164.all;

entity mux is

port (a,b,c,d,e,f,g,h, clk, reset : in std_logic;
       S : in std_logic_vector (2 downto 0);
       q, q_n : out std_logic);
end entity;

architecture mux_arch of mux is

component OBUF_LVDS port (
      I : in std_logic;
      O : out std_logic);
end component;


signal a_int, q_int, mux_out, mux_out_n, muxout_n_reg : std_logic;

begin

process (a,b,c,d,e,f,g,h,s)
begin

   case S is
     when "000" =>
      q_int<=a;
     when "001"=>
      q_int<=b;
     when "010" =>
      q_int<=c;
     when "011" =>
      q_int<=d;
     when "100" =>
      q_int<=e;
     when "101" =>
      q_int<=f;
     when "110" =>
      q_int<=g;
     when "111" =>
      q_int<=h;
     when others =>
          q_int<='X';
   end case;
end process;

process (clk, reset)
begin
if (reset='1') then
    mux_out<='0';
elsif (clk'event and clk='1') then
      mux_out<=q_int;
end if;
end process;
mux_out_n <= not q_int;

process (clk, reset)
begin
if (reset='1') then
    muxout_n_reg<='1';
elsif (clk'event and clk='1') then
    muxout_n_reg<=mux_out_n;
end if;
end process;

U1 : OBUF_LVDS port map(I=>mux_out, O=>q);
U2 : OBUF_LVDS port map(I=>muxout_n_reg, O=>q_n);

end mux_arch;

Here is the ucf constraints:

net q LOC=P20;
net q_n loc=P21;
net a LOC=P169;
net b LOC=P168;
net c LOC=P167;
net d LOC=p163;
net e LOC=p162;
net f loc=p161;
net g loc=p160;
net h loc=p159;
net clk loc=p210;
net reset loc=P157;
net s(0) loc=p156;
net s(1) loc=p155;
net s(2) loc=p154;

Make sure map -pr o option is used to ensure the FFs being pushed
inside IO block.




End of Record #8187 - Last Modified: 12/09/99 11:56

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!