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FPGA Configuration: Startup sequence has not yet completed
Record #8196
Problem Title:
FPGA Configuration: Startup sequence has not yet completed
Problem Description:
Urgency: Standard
General Description:
During configuration, it is possible that the FPGA will receive all
configuration data correctly, but will still fail to finish the configuration
sequence. In this case, it is most likely due to the fact that the
startup sequence has not yet been completed.
Solution 1:
To complete the STARTUP Sequence all that is needed are a few more
clock cycles. The clock signal that is used for the STARTUP state
machine is the CCLK by default. However, another (USER or JTAG) clock may be
specified by using the STARTUP component in the design and selecting
the startup clock options for bitstream generation. Be sure which has been
selected for your design implementation and assert the clock. The bitgen.ut
file lists the bitgen options used (if the GUI is used).
Solution 2:
Another possibility is that the DONE pin is being held low externally, or is not
being pulled up. The DONE pin is an Open-Drain driver that must be pulled
up to achieve a logic high. While the FPGA does have a programmable
internal pullup resistor to the DONE pad, we recommend using an external
4.7Kohm resistor for all 4000/5200 series devices, or an external 300ohm
resistor for all Virtex devices. If necessary, seperate the DONE pin from the
board to verify if an external source is holding it low.
End of Record #8196 - Last Modified: 01/12/00 11:49 |
