Answers Database
FPGA Configuration: Configuration data is incorrect
Record #8197
Problem Title:
FPGA Configuration: Configuration data is incorrect
Problem Description:
Urgency: Standard
General Description:
If the configuration data is incorrect, the FPGA will never properly configure.
There are a number of things that one can do to determine if this is the case.
Solution 1:
4000/Spartan/5200 families
It is highly unlikely that the loading of incorrect configuration data would not
result in a DataFrame ERROR (INIT goes low); however, if the Preamble
sequence <0010> is never observed by the FPGA then the configuration
process would never have started. Thus, no error would be detected.
Check to see if the data is backwards. If the configuration data is being
accessed in byte words and shifted serially into the FPGA then shifting in the
wrong direction would result in observing <0000 0100> instead of
<0010 0000> on DOUT.
If the data is simply incorrect then this is most likely a result of a problem in the
application board or timing specification requirements not properly met.
Solution 2:
Virtex families
The Virtex family does not produce any output on DOUT during configuration
as the 4000 series did, however, there is a syncronization word that must be
loaded before configuration begins.
First verify that the 32 bit syncronization word (0xAA995566) is being properly
passed into the device. Once the correct data into the device has been
verified, it is now possible to verify that the Virtex device received the
information correctly. (Xilinx Solution 7891) documents this process in detail.
End of Record #8197 - Last Modified: 01/12/00 11:50 |
