Answers Database
EXEMPLAR: How to instantiate LUT primitives in HDL for Virtex?
Record #8207
Product Family: Software
Product Line: Exemplar
Product Part: Exemplar
Product Version: 4.1.3
Problem Title:
EXEMPLAR: How to instantiate LUT primitives in HDL for Virtex?
Problem Description:
Urgency: Standard
General Description:
How to instantiate LUT primitives in HDL for Virtex using
Exemplar's Leonardo Spectrum?
You can instantiate the LUT* cells by using the Xilinx family
library information built into Exemplar.
LUT1, LUT2, LUT3, and LUT4 are, respectively, 1-, 2-, 3-, and
4-bit look-up-tables (LUTs) with general output (O).
A mandatory INIT attribute, with an appropriate number of
hexadecimal digits for the number of inputs, must be
attached to the LUT to specify its function.
NOTE: Tested with Exemplar Spectrum 1999.1g
Solution 1:
Verilog Example:
After reading the code in Exemplar, the INIT
attributes must be set for each instantiated LUT. For the
example below, use the following commands to pass the
INIT attributes from the Exemplar command line:
set_attribute -instance U0 -name INIT -type string -value "01"
set_attribute -instance U1 -name INIT -type string -value "10"
set_attribute -instance U2 -name INIT -type string -value "1000"
set_attribute -instance U3 -name INIT -type string -value "0111"
------
module lut_ex (LUT1_OUT, LUT1_IN, LUT2_OUT, LUT2_IN);
input [1:0] LUT1_IN, LUT2_IN;
output [1:0] LUT1_OUT, LUT2_OUT;
// LUT1 used as an inverter
LUT1 U0 (.O (LUT1_OUT[0]), .I0 (LUT1_IN[0]));
// LUT1 used as a buffer
LUT1 U1 (.O (LUT1_OUT[1]), .I0 (LUT1_IN[1]));
// LUT2 used as a 2-input AND gate
LUT2 U2 (.O (LUT2_OUT[0]), .I1 (LUT2_IN[1]), .I0 (LUT2_IN[0]));
// LUT2 used as a 2-input NAND gate
LUT2 U3 (.O (LUT2_OUT[1]), .I1 (LUT2_IN[1]), .I0 (LUT2_IN[0]));
endmodule
Solution 2:
VHDL Example:
After reading the code in Exemplar, the INIT
attributes must be set for each instantiated LUT. For the
example below, use the following commands to pass the
INIT attributes from the Exemplar command line:
set_attribute -instance u0 -name INIT -type string -value "01"
set_attribute -instance u1 -name INIT -type string -value "10"
set_attribute -instance u2 -name INIT -type string -value "1000"
set_attribute -instance u3 -name INIT -type string -value "0111"
----
library ieee;
use ieee.std_logic_1164.all;
library virtex;
use virtex.components.all;
entity lut_ex is
port (
LUT1_IN, LUT2_IN : in std_logic_vector(1 downto 0);
LUT1_OUT, LUT2_OUT : out std_logic_vector(1 downto 0));
end entity lut_ex;
architecture XILINX of LUT_EX is
component LUT1
port (O : out std_logic;
I0 : in std_logic);
end component;
component LUT2
port (O : out std_logic;
I0, I1 : in std_logic);
end component;
begin
-- LUT1 used as an inverter
U0 : LUT1
port map (O => LUT1_OUT(0), I0 => LUT1_IN(0));
-- LUT1 used as a buffer
U1 : LUT1
port map (O => LUT1_OUT(1), I0 => LUT1_IN(1));
-- LUT2 used as a 2-input AND gate
U2 : LUT2
port map (O => LUT2_OUT(0), I1 => LUT2_IN(1), I0 => LUT2_IN(0));
-- LUT2 used as a 2-input NAND gate
U3 : LUT2
port map (O => LUT2_OUT(1), I1 => LUT2_IN(1), I0 => LUT2_IN(0));
end XILINX;
End of Record #8207 - Last Modified: 12/13/99 18:23 |
