Answers Database
FPGA Configuration : DONE pin is being held low externally
Record #8241
Problem Title:
FPGA Configuration : DONE pin is being held low externally
Problem Description:
Urgency: Standard
General Description:
The DONE Pin is being held Low externally.
Solution 1:
The DONE pin is an Open-Drain driver that must be pulled
up to achieve a logic high. While the FPGA does have a
programmable internal pullup resistor to the DONE pad, we
recommend using an external 4.7Kohm resistor. If necessary,
seperate the DONE pin from the board to verify if an external
source is holding it low.
If the DOUT has gone High then the DONE pin must have
been released internally. Double check the STARTUP sequence
options selected for Bitstream generation. The SyncToDone is
recommended, and required if multiple FPGAs are Daisy-Chained
in Serial or Express Mode Configuration. The SyncToDone prevents the
STARTUP sequence from continuing (ie I/Os become active)
until the DONE pin is externally allowed to pull High. If the FPGA is
Daisy-Chained then the DONE is probably being held Low by one
of the other FPGAs. The recommended STARTUP Options are
(for 3000, 4000, and 5200 series devices)
DONE:C1
OutputsActive:DI
GSRinactive:DI
and for Virtex and Virtex derivatives:
DONE_cycle:4
GTS_cycle:5
GSR_cycle:6
GWE_cycle:6
Note: These options may need to be altered depending on the system topology.
End of Record #8241 - Last Modified: 12/21/99 13:02 |
