Answers Database


2.1i Virtex PAR - Application Error during Placement of V300 design


Record #8251

Product Family: Software

Product Line: FPGA Implementation

Product Part: par

Product Version: 2.1i

Problem Title:

2.1i Virtex PAR - Application Error during Placement of V300 design


Problem Description:
Urgency: Standard

Problem Description:
A V300 design that utilizes 100% of the device is causing the Placer to Application error. Trying a larger part allows PAR to complete successfully.

This problem was found to be due to an F5 --> F5IN connection where
the F5 driver is contained within a macro, but the F5IN load is not. This
situation is similar to carry chain placement where the placer can only
handle cases where eith all slices are LOC'd or all slices are un-LOC'd.


Solution 1:

A fix will be included in the next major release (due in May, 2000) so that
PAR will error out with a description of the problem rather than crashing.




End of Record #8251 - Last Modified: 01/31/00 10:40

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!