Answers Database
2.1i 4KXLA Map - FATAL_ERROR:OldMap:x45maclb.c:204:1.1.2.2 - Unknown input pin Q
Record #8262
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Product Version: 2.1i
Problem Title:
2.1i 4KXLA Map - FATAL_ERROR:OldMap:x45maclb.c:204:1.1.2.2 - Unknown input pin Q
Problem Description:
Urgency: Standard
General Description:
A case has been seen where a netlist can be mapped successfully
into a 4KXL part, but map fails with the following error when targeting
a 4KXLA part:
FATAL_ERROR:OldMap:x45maclb.c:204:1.1.2.2 - Unknown input pin Q for
CLB LATCH primitive. Process will terminate.
Solution 1:
All the pin types in the LDCE_1 latches were incorrectly defined to be "B" instead of "I"
or "O". LDCE_1 is not listed as a primitive in the FPGA Express library. Because of this, it
is treated as a black box when it is instantiated. Verilog does not require pin directions to
be defined for these types of instantiations, and since Express has no knowledge of this
component, it will default to Bidirectional. To solve this problem, simply define the LDCE_1
module like this:
module LDCE_1 (G,CLR,GE,D,Q);
input G,CLR,GE,D;
output Q;
endmodule
It will still be instantiated as a black box to be expanded by ngdbuild, but you will see that the p
in
directions are declared properly in the resulting XNF.
The reason the design behaved differently in 4KXL vs.4KXLA is that the LDCE_1
is a primitive for the 4KXLA whereas for the 4KXL, a lower level LDCE is pulled in
with valid pin types.
End of Record #8262 - Last Modified: 12/14/99 17:50 |
