Answers Database
Virtex CLKDLL VHDL simulation: DLL outputs are not toggling (No output) CLKIN is delayed
Record #8263
Product Family: Software
Product Line: Merged Core
Product Part: univhd
Problem Title:
Virtex CLKDLL VHDL simulation: DLL outputs are not toggling (No output) CLKIN is delayed
Problem Description:
Urgency: Stanrdard
General Description:
I am using the CLKDLL and doing a VHDL backend timing simulation
using the Xilinx 2.1i tools. The CLKIN to the DLL is delayed for
hundreds of nano-seconds, or has a signal that is much slower than
the specified frequency range for the DLL for hundredes of nano-
seconds. After this amount of time CLKIN changes to a frequency
within the range of the DLL, but the outputs are all stuck, and the
output such as CLK0, and CLK2X are not toggling.
Solution 1:
This is a simprim CLKDLL model problem. There is a wait statement
that the model is getting stuck in when the CLKIN pin is stimulated as
described. Line 1841 can be commented out in the file
simprim_VITAL.vhd. The line reads:
wait;
This will be fixed in the next major release of the Xilinx software.
End of Record #8263 - Last Modified: 01/10/00 15:45 |
