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Virtex-E datasheet: What are the pins for LVDS global clocks?


Record #8341

Problem Title:
Virtex-E datasheet: What are the pins for LVDS global clocks?


Problem Description:
Urgency: standard

General Description:
As mentioned in the datasheet (December 7, 1999):
http://support.xilinx.com/partinfo/ds022.pdf
Example package BG 432 (page 56):

GCLK BANK P-pin N-pin	 Other Functions
0	 4	   AL16 AH15   IO_DLL_L86P
1	 5	   AK16 AL17   IO_DLL_L86N
2	 1	   A16 B16	  IO_DLL_L16P
3	 0	   D17 C17	  IO_DLL_L16N

What the the N and P sides of the LVDS pairs, and how many are there?


Solution 1:

There are 4 pairs of LVDS clock pins in VirtexE devices. The global clock pins
are always the positive side of the LVDS pair. The adjacent IO pins to the global clock pins are the negative side of the LVDS pair.




End of Record #8341 - Last Modified: 12/27/99 09:45

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