Answers Database
FPGA Configuration: Why doesn't the parallel cable have an INIT pin?
Record #8342
Problem Title:
FPGA Configuration: Why doesn't the parallel cable have an INIT pin?
Problem Description:
Urgency:
Standard
General Description:
Page 6-50 of the 99 databook, clearly shows that the INIT pin states
when the clearing of configuration memory is done.
So why doesn't the parallel cable have the INIT pin to determine this status?
Solution 1:
The parallel cable pulses PROG low and then waits a certain amount of
time before sending DATA to the device. This wait is longer than the time
needed for the device to clear its configuration memory and hence the
step in the flowchart is done this way without concerning the INIT pin.
The INIT pin is NOT monitored by the cable to see if there was any error.
The only way the cable knows anything is if it waits for DONE to go high
and times out. The user will have to check if INIT is low separately to
determine if a frame error was the cause of the problem.
End of Record #8342 - Last Modified: 12/27/99 09:26 |
