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Foundation 2.1i: Timing simulation of Virtex DLL fails when input frequency is higher than 100MHz
Record #8398
Problem Title:
Foundation 2.1i: Timing simulation of Virtex DLL fails when input frequency is higher than
100MHz
Problem Description:
Urgency: High
General Description: When performing a timing simulation of a Virtex CLKDLL,
the CLKDLL functions properly to a specified clock frequency, then fails to output
the correct or any frequency.
This result is caused by lump sum modeling.
Solution 1:
This can be resolved in two ways:
1- Use a simulator that supports transport or transparent switches. This will allow the
small clock pulses to pass through the logic, causing the CLKDLL to simulate correctly.
2- Set the following environment variable: XIL_PP_OPTIMIZE to true.
End of Record #8398 - Last Modified: 02/02/00 15:46 |
