Xilinx Answer #8406 : 2.1i Virtex Constraints Editor: Drive strength constraints is ignored. (FPGA Express only)

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2.1i Virtex Constraints Editor: Drive strength constraints is ignored. (FPGA Express only)

Record #8406
Product Family: Software

Product Line: FPGA Implementation

Product Part: NGDBuild

Product Version: 2.1i

Problem Title:

2.1i Virtex Constraints Editor: Drive strength constraints is ignored. (FPGA Express only)

Problem Description:
Urgency: Standard

Problem Description:

After specifying Drive Strength or Slew Rate from the pull down menu's for a specific outout in Constraints Editor, the constraint is ignored after implementation.

Solution 1:

This is a know issue with Synopsys FPGA Express design. After specifying a constraint in the constraint editor, the contraint is written into the constraint file.

For example, the syntax for a drive strength of 4 is:

NET <output portname> DRIVE=4;

fpga_express writes out the edif file with OBUF_S_12 by default, instead
of just an OBUF. After you set NET netname DRIVE=4 attribute in the
constraint file, what happens in the NGD file after running NGDBuild is that
the OBUF instance still uses DRIVE=12, but the OPAD instance uses DRIVE=4ma;
MAP only picks up the constraint on the OBUF, not the OPAD.

The workaround is to place the constraints on the OBUF instance. In the
.UCF file, place:

INST C_<pad name> DRIVE = 4;

The C_ is the OBUF instance name for nets synthesized in Express.

This problem will be fixed in the next major release.

End of Record #8406 - Last Modified: 01/14/00 13:54

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