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Virtex: VHDL and Verilog code for select link application
Record #8483
Problem Title:
Virtex: VHDL and Verilog code for select link application
Problem Description:
Urgency: Standard
General Description:
At http://www.xilinx.com/applications/slcv/selectlink.htm you can get
a Verilog code for select link application for Virtex devices.
Currently there are no plans from Xilinx to add a VHDL code generator as well.
Solution 1:
Most synthesis/simulation tools can translate both, Verilog and VHDL.
So as a workaround you can instantiate the generated Verilog macro
in your VHDL design.
Solution 2:
If your synthesis/simulation tool can't translate VHDL and Verilog you have to
translate the Verilog code into VHDL.
End of Record #8483 - Last Modified: 02/14/00 09:17 |
