File Archive: sw_synopsys
Contents of /pub/swhelp/synopsys
Files/Patches/Information on the Xilinx-Synopsys Interface (XSI)
**Note** For XSI documentation and added information about using
the FPGA and Design Compiler please refer to the Synopsys
FPGA Compiler Interface Web Journal at
http://www.xilinx.com/support/techsup/journals/synopsys/index.htm
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Filename Size File Description
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40125_synlibs.tar.Z
2690 Kb Uploaded: 09-10-1998
This file contains the A1.4 XSI 40125XV
synthesis librariess, which can be used with
Synopsys v1997.01 or later. These libraries are
to be used with the FPGA Compiler/Design
Compiler tools.
Solution #: 4570
For All Unix
SW Release: A1.4
Category: SW Update, Libraries
Dependencies: For use with A1.4 only.
40150_synlibs.tar.Z
2916 Kb Uploaded: 03-02-1999
This file contains the A1.5i XSI 40150XV-09
synthesis librariess, which can be used with
Synopsys v1998.08 or later. These libraries are
to be used with the FPGA Compiler/Design
Compiler tools.
Solution #: 5777
For All Unix
SW Release: A1.5i
a15_xsi_xla.tar.gz
1403 Kb Uploaded: 12-11-1998
This file contains the updated A1.5 XSI 4000XLA-
09 synthesis libraries and M1 run files, which
can be used with Synopsys v1997.01 or later.
These files are meant to be used with the FPGA
Compiler/Design Compiler tools.
Solution #: 4489
For All Unix
SW Release: A1.5i/F1.5i
Category: SW Update, Libraries
a15xsi_virtex.tar.gz 833 Kb Uploaded: 09-23-1998
Updated Virtex libraries for use with Synopsys
FPGA Compiler or Design Compiler and the Xilinx
Alliance 1.5 release of software.
Solution #: 4666 & 4671
For All Unix
SW Release: A1.5
Category: SW Update, Libraries
addmaketnm.tar.Z 13 Kb Addtnm version 2.3.4 and Maketnm
version 2.3.3 perl script
utilities for adding timespecs
to xnf files
Solution #: 1207
For All UNIX
ext2sig.zip 1 Kb ext2sig.pl Perl script for XNF modules generated
by FPGA Express v1.2. This tool is not required.
Solution #: 2843
For Win 95, Win NT 4.0
Uploaded: 10-24-97
fe_ctl.zip 0 Kb Patch file for Alliance version of FPGA Express
2.0. Fixes crashes due to certain HDL
constructs.
Solution #: 3308
For Win 95, Win NT 4.0
Uploaded: 01-16-98
m1412_9701_dw.tar.Z 6707 Kb M1.4 XDW FPGA and CPLD libraries compiled for
Synopsys v1997.01. These compiled XDW libraries
can be used with any FPGA Compiler/Design
Compiler on any UNIX OS.
Solution #: 1166
For All Unix
Uploaded: 01-25-98
m1412_9708_dw.tar.Z 7302 Kb M1.4 XDW FPGA and CPLD libraries compiled for
Synopsys v1997.08. These compiled XDW libraries
can be used with any FPGA Compiler/Design
Compiler on any UNIX OS.
Solution #: 1166
For All Unix
Uploaded: 01-25-98
m1412_9802_dw.tar.Z 8283 Kb M1.4 XDW FPGA and CPLD libraries compiled for
Synopsys v1998.02. These compiled XDW libraries
can be used with any FPGA Compiler/Design
Compiler on any UNIX OS.
Solution #: 1166
For All Unix
SW Release: 1.4
Uploaded: 05-04-98
m15_9708_dw.tar.gz
5315 Kb Uploaded: 10-19-1998
A1.5 Xilinx Designware (XDW) FPGA and CPLD
libraries compiled for Synopsys v1997.08 of FPGA
Compiler or Design Compiler. Includes fix for
ADD_SUB carry chain problem.
Solution #: 1166, 4809
For All Unix
SW Release: A1.5
Category: SW Update, Libraries
m15_9802_dw.tar.gz
5314 Kb Uploaded: 10-19-1998
A1.5 Xilinx Designware (XDW) FPGA and CPLD
libraries compiled for Synopsys v1998.02 of FPGA
Compiler or Design Compiler. Includes fix for
ADD_SUB carry chain problem.
Solution #: 1166, 4809
For All Unix
SW Release: A1.5
Category: SW Update, Libraries
m15_9808_dw.tar.gz
5310 Kb Uploaded: 10-19-1998
A1.5 Xilinx Designware (XDW) FPGA and CPLD
libraries compiled for Synopsys v1998.08 of FPGA
Compiler or Design Compiler. Includes fix for
ADD_SUB carry chain problem.
Solution #: 1166, 4809
For All Unix
SW Release: A1.5
Category: SW Update, Libraries
m15_dw_src.tar.gz
861 Kb Uploaded: 12-08-1998
1.5 Xilinx Designware (XDW) FPGA and CPLD source
libraries for Synopsys FPGA Compiler and/or
Design Compiler. Includes fix for ADD_SUB carry
chain problem. These files must be analyzed by
Synopsys before using for synthesis.
Solution #: 1166, 4809
For All Unix
SW Release: A1.5
Category: SW Update, Libraries
m1_1412_35a_dw.tar.Z 6701 Kb M1.4 XDW FPGA and CPLD libraries compiled for
Synopsys v3.5a. These compiled XDW libraries can
be used with any FPGA Compiler/Design Compiler
on any UNIX OS.
Solution #: 1166
For All Unix
Uploaded: 01-25-98
m1_2_9701_dw.tar.Z 4185 Kb Analyzed M1_2 designware synthesis libraries for
Synopsys FPGA and Design Compiler Version
1997.01. To install: Copy this file to your
$XILINX directory and unarchive the file. See
README for details.
Solution #: 1166
For All Unix
Uploaded: 06-25-97
m1_3_35a_dw.tar.Z 7820 Kb Analyzed M1_3 designware synthesis libraries for
Synopsys FPGA and Design Compiler Version 3.5a.
To install: Copy this file to your $XILINX
directory and unarchive the file. See README for
details.
Solution #: 1166
For All Unix
Uploaded: 08-01-97
m1_3_9701_dw.tar.Z 7825 Kb Analyzed M1_3 DesignWare synthesis libraries for
Synopsys FPGA and Design Compiler Version
1997.01. To install: Copy this file to your
$XILINX directory and unarchive the file. See
README for details.
Solution #: 1166
For All Unix
Uploaded: 08-08-97
m1_3_9708_dw.tar.Z 8404 Kb Analyzed M1_3 DesignWare synthesis libraries for
Synopsys FPGA and Design Compiler Version
1997.08. To install: Copy this file to your
$XILINX directory and unarchive the file. See
README for details.
Solution #: 1166
For All Unix
Uploaded: 01-23-98
m1_xsi_hdl.tar.Z 13034 Kb Synopsys (XSI) Synthesis and Simulation Design
Guide. This is a manual to assist Synopsys FPGA
Compiler I users to design into FPGAs using the
M1 software. This manual includes design
hints(Verilog and VHDL), synthesis tips and
simulation techniques
For All Platforms
SW Release: All M1
Uploaded: 05-05-98
m1_xsi_hdl.zip 7683 Kb Verilog and VHDL example files to accompany the
Synopsys (XSI) Synthesis and Simulation Design
Guide (for M1). Source, script and all design
files.
For All Platforms
Uploaded: 01-20-98
m1_xsi_verilog.tar.Z 5128 Kb Verilog example files to accompany the Synopsys
(XSI) Synthesis and Simulation Design Guide (for
M1). Source, script and all design files.
For All Platforms
Uploaded: 01-20-98
m1_xsi_verilog.zip 3545 Kb Verilog example files to accompany the Synopsys
(XSI) Synthesis and Simulation Design Guide (for
M1). Source, script and all design files.
For All Platforms
Uploaded: 01-20-98
m1_xsi_vhdl.tar.Z 6181 Kb VHDL example files to accompany the Synopsys
(XSI) Synthesis and Simulation Design Guide (for
M1). Source, script and all design files.
For All Platforms
Uploaded: 01-20-98
m1_xsi_vhdl.zip 4169 Kb VHDL example files to accompany the Synopsys
(XSI) Synthesis and Simulation Design Guide (for
M1). Source, script and all design files.
For All Platforms
Uploaded: 01-20-98
m21_9708_dw.tar.gz
28410 Kb Uploaded: 09-27-1999
A2.1i Xilinx Designware (XDW) FPGA and CPLD
libraries compiled for Synopsys v1997.08 of FPGA
Compiler or Design Compiler.
Solution #: 7000
For All Unix
SW Release: A2.1i
m21_9802_dw.tar.gz
27940 Kb Uploaded: 09-27-1999
A2.1i Xilinx Designware (XDW) FPGA and CPLD
libraries compiled for Synopsys v1998.02 of FPGA
Compiler or Design Compiler.
Solution #: 7000
For All Unix
SW Release: A2.1i
makeucf2.tar.Z
3 Kb Uploaded: 08-10-1999
makeucf was designed to replace addtnm/maketnm.
makeucf allows a designer to create a UCF file
if the design was compiled with FPGA Compiler
and produced a SXNF file for a XC4000X FPGA.
This version is modified slightly to match
instructions listed in XAPP107.
Solution #: 4491
For All Unix
SW Release: All M1
numeric_std_a.zip
13 Kb Uploaded: 12-15-1999
NUMERIC_STD.VHD library for FPGA Express 3.1 or
3.2 only (Foundation Express F1.5i with Service
Pack 1)
Solution #: 5432
For All Windows
SW Release: A1.5i/F1.5i
xbloxgen115.tar.Z 27 Kb xbloxgen version 1.15 utility
which allows you to instantiate
X-BLOX components
Solution #: 1200, 1201
xprsdgde.zip 124 Kb Synopsys FPGA Express Design
Guide v1.0
For All Windows
Uploaded: 02-24-97
xsi521.4ke-4.tar.Z 1192 Kb XSI 5.2.1 4ke-4 .db Files
Uploaded: 10-04-96
xsi521.9701_dw.tar.Z 10885 Kb Analyzed 5.2.1 designware and simulation
libraries for Synopsys FPGA and Design Compiler
Version 1997.01-44683. To install: Copy this
file to your $DS401 directory and unarchive the
file. See README for details.
For All Unix
Uploaded: 07-03-97
xsi521.synopsys33b.tar.Z Compiled 5.2.1 Designware and
Simulation Libraries for
Synopsys 3.3b
Solution #: 1166
Uploaded: 10-04-96
xsi521.synopsys34a.tar.Z Compiled 5.2.1 Designware and
Simulation Libraries for
Synopsys 3.4a
Solution #: 1166
Uploaded: 10-04-96
xsi521.synopsys34b.tar.Z Compiled 5.2.1 Designware and
Simulation Libraries for
Synopsys 3.4b
Solution #: 1166
Uploaded: 10-04-96
xsi521.synopsys35a.tar.Z XSI 5.2.1 DesignWare and Simulation
Libraries Compiled for Synopsys 3.5a
For All UNIX Systems
Uploaded: 11-18-96
xsi521_31a.tar.Z 514 Kb XSI 5.2.1 .db synthesis files for the
XC3100A -1 & -09 speeds. These .db files are
to be used with XSI 5.2.1, and Synopsys 3.3b
and above.
For All UNIX Systems
Solution #: 1709
Uploaded on Thu Jan 16 20:04:12 PST 1997
xsi521_4ke-2.tar.Z 1051 Kb XSI 5.2.1 .db synthesis files for the
XC4000E -2 speeds. These .db files are
to be used with XSI 5.2.1, and Synopsys 3.3b
and above.
For All UNIX Platforms
Solution #: 1708
Uploaded: 01-16-97
xsi521_9708.tar.Z 8120 Kb XSI 5.2.1 XBLOX and VSS simulation libraries
compiled for Synopsys v1997.08.
Solution #: 1166
For All Unix
Uploaded: 11-04-97
xsi521_syn33b_5k.tar.Z 901 Kb XSI 5.2.1 5210-4, 5215-5, 5215-6 .db files
These files are compatible with
XSI 5.2.1 and Synopsys 3.3b or greater
For All UNIX Systems
Uploaded: 10-31-96
xsi_files.tar.Z 83 Kb * Tactical Code
* XNF Files for RPMs
* Default Synopsys setup file
xsi_hdl_dg.pdf 1380 Kb Synopsys (XSI) Synthesis and Simulation Design
Guide. This is a manual to assist Synopsys FPGA
Compipler users to design into FPGAs using the
M1 software. This manual includes design
hints(Verilog and VHDL), synthesis tips and
simulation techniques
For All Platforms
SW Release: All M1
Uploaded: 04-23-98
xsi_verilog.tar.Z 2974 Kb Verilog Examples from HDL
Synthesis for FPGAs Design
Guide
xsi_vhdl.tar.Z 5115 Kb VHDL Examples with SIM, SYN
and MRA files in Work directory
xsi_vhdl_no_wk.tar.Z 3253 Kb VHDL Examples without SIM,
SYN and MRA files in Work
directory
