Ask Sparty is a set of questions and answers about the Spartan-II Family of FPGAs. Select from the topic categories below. If you don't find the answer to your question, check our support web site for more technical information, or contact your local Xilinx sales office.

Index

H-N O-Z A-G AllianceCORE Bitstream Devices DLL FFT H-N Install IOB IRL JTAG Configuration Literature LogiCORE Mode pins ngdbuild error O-Z Packages Process Samples Spartan Series Speed Temperature Virtex Voltage

What's New? Can the Spartan-XL Device Run at Below 3.0V and/or Above 100°C? What are the differences between Spartan-II engineering samples and the production product, regarding JTAG? Can the Spartan-II devices be configured through the JTAG port? How can the Spartan-II DLL be used to multiply the frequency of a clock signal by a factor of four?

Introduction What is the Spartan-II family? What process technology is the Spartan-II family designed in? What are the devices in the family? What operating voltage will the Spartan-II family perform to? Is the speed naming convention the same for the Spartan-II family as it was for the Spartan and Spartan-XL family?

Availability What are the differences between Spartan-II engineering samples and the production product, regarding JTAG? What are the available packages? What are the available cores for the Spartan-II family? What various temperature grades will be available for the Spartan-II family?

Literature What literature is available on the Spartan-II Series? How can I request literature from Xilinx?

Architecture Can the Mode pins be driven High after Boundary Scan configuration? What are the differences between Spartan-II engineering samples and the production product, regarding JTAG? Can the Spartan-II devices be configured through the JTAG port? How can the Spartan-II DLL be used to multiply the frequency of a clock signal by a factor of four? What are the differences between the Spartan-II family and Spartan-XL family? Are Spartan-II FPGAs pin-to-pin compatible to prior Spartan Series product offerings? Is the new Spartan-II family footprint compatible with the Virtex family devices? What are the differences between the Spartan-II family and the Virtex family since the two are based on the same architectures? What are the architectural differences between the Spartan-II, Spartan-XL and Spartan families of FPGAs? What routing advantages does the Virtex architecture provide for the Spartan-II family? Are the Spartan-II devices bitstream compatible with the Virtex devices?

Software How do I access software support for the Spartan-II Family? What software supports the Spartan-II family? Will the Spartan-II family have the capability to support Internet Reconfigurable Logic (IRL)? What are the available cores for the Spartan-II family? Why does running a design with either BSCAN_SPARTAN2, CAPTURE_SPARTAN2 or STARTUP_SPARTAN2 generate an "unexpanded" error in ngdbuild? How can place and route results be improved without using timing constraints? How do I access special IOB components in FPGA Express?

Core Solutions What are the available cores for the Spartan-II family? What are LogiCORE solutions? What are AllianceCORE solutions? Do the Xilinx FFT Cores support the Spartan-II architecture?