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Frequently Asked Questions - Xilinx 32-Channel HDLC
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Q1) Do I have to use all 32 channels of the core?
A1) No, only those channels required for the system need
be addressed and hence used in the core.
Q2) Is the core data rate 40 Mb/s per channel?
A2) No, the total data rate is 40 Mb/s, this should be divided
by the number of channels being used to get the rate per channel.
Integrating the core on a faster device or using more stringent timing and
placement constraints will allow this data rate to be increased.
Q3) Do I need to use off-chip RAM with the HDLC32 core?
A3) No, all the RAM required by the core has been integrated in on-chip RAM.
Q4) How do I integrate the core into my system design?
A4) Using the template provided (HDLC32.vho or HDLC32.veo) instantiate the
core within your system code. Place the core edif netlist in your
synthesis directory. Synthesizing your system code will instantiate the
core as a 'black-box' component in the output edif netlist. Running
'Program Manager' on the output netlist will incorporate the core netlist
into the design automatically.
Q5) Is the LogiCore HDLC bit stuffed or Byte stuffed?
A5) The LogiCore HDLC controller is bit stuffed. Between frame flags,
sequences of five numerical ones will have an extra zero automatically inserted (Tx) or
removed (Rx).
Q6) Is the core fully synchronous?
A6) The core is synchronized to the PCM highway clock, i.e. the core is
synchronous with the serial data bit rate.
Q7) How do I select a channel?
A7) Driving the RxChannel or TxChannel signal with the required channel
value will set the active channel on the next clock tick. All the other
core inputs and outputs relate to the channel which is currently active,
i.e. was present on TxChannel or RxChannel on the previous tick.
Q8) Can I instantiate more than one HDLC-32 core for higher channel counts?
A8) Yes - Use the TxEN and RxEN signals to stall the non-selected HDLC-32
Core. An external mux is necessary to select which of the TxD signals
drives the serial bus.
Q9) How do I send a frame?
A9) Configure the channel's Address register and enable the HDLC protocol.
Drive the data for the first data byte of the frame for the selected
channel on TxFrameData along with TxFrameStart. Once TxDataStrobe is
asserted on a tick when that channel is selected, the frame will have
started. Drive the next data byte on TxFrameData until TxDataStrobe is
seen again, and so on. For the last byte, assert TxFrameEnd at the same
time as driving the last data byte.
Q10) What's the limit on frame size (MTU)?
A10) There is no limit in the HDLC core. The data part of a frame can be any size.
Q11) How are corrupted frames indicated?
A11) The receiver asserts RxFrameEnd, RxDataStrobe and the last data byte on
RxDataOut at the end of every frame. If the FCS field indicates the frame
was corrupted during transmission, then RxFrameError is also asserted at
this time.
Q12) How can I select between transmitting the Idle sequence and empty frames
when I have no data to send?
A12) The HDLC core will only transmit idle sequence (all ones) when the HDLC
protocol is disabled in the Tx Control Register. If HDLC is enabled, then
back to back flags (empty frames) will be sent in the absence of any
data. The receiver core can handle either type of inter frame fill.
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