Xilinx T1/E1 Solutions

Xilinx T1/E1 Solutions

The T1/E1 cores are optimized, low cost, CCITT compliant solutions to accelerate product time-to-market for communications applications. T1/E1 Framer and T1 Deframer Cores for Virtex, Virtex-E and Spartan-II T1/E1 Solutions available now for prices below ASSPs
	T1/E1 Lounges (Customers only) Registration for the T1/E1 Framer Registration for the T1 Deframer Download the Xilinx T1E1 Framer core Download the Xilinx T1 Deframer core

Overview

Xilinx provides fixed netlist LogiCORE solutions for both the T1/E1 Framer and T1 Deframer cores for communications applications. By using a Xilinx T1/E1 solution, users can significantly reduce implementation cost and accelerate time-to-market compared to fixed function Application Specific Standard Product (ASSP) alternatives.

The cores are available immediately and support Xilinx Virtex, Virtex-E and Spartan-II FPGA families. These new cores create an ideal solution for many telecommunication system applications such as ISDN Primary Rate Access links, multiplexing equipment, satellite communications, digital

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Spartan-II Logo

The Basics of T1/E1 Transmission Interfaces

T1/E1 interfaces are required throughout the network, anywhere there is a connection to a T1 or E1 trunk. T1 is a standard for digital transmission in North America and Japan and has a total signaling speed of 1.544 Mbps. E1 is the European equivalent and runs at a total signaling rate of 2.048 Mbps. The T1/E1 Framer generates a T1 or E1 frame and the enables for each of the bits in the frame. The Deframer locks on to the start of the frame and then generates an enable for each of the bits inside a frame.

T1/E1 Framer LogiCore Features
Generates muliple frame structures T1-D4, T1-ESF and E1 frames Fully compliant with CCITT Recommendation G.704 (G.706, G.732, G.733) Programmable idle codes for data and signalling Provides support for CRC6 and CRC4 generation Provides bit location output signals Fully synchronous design Optimized for Virtex, Virtex-E and Spartan-II architectures	a Xilinx AllianceCORE partner

T1 Deframer LogiCORE Features

Supports T1-D4 and T1-ESF frame structures
Fully compliant with CCITT Recommendation G.704 (G.706, G.733)
Provides support for recovering & inserting robbed bit signalling
Provides support for recovering and generating CRC6
Provides support for recovering and inserting serial data link (ESF only)
Full detection of yellow alarm condition
FAW bit error monitoring allows BER estimation
Fast frame alignment time
Fully synchronous design
Optimized for Virtex, Virtex-E and Spartan-II architectures

Implementation Examples

Target Device T1/E1 Framer	Virtex XCV200-6	Virtex-E XCV200E-8	Spartan-II XC2S150-6
Size	128 Slices	128 Slices	128 Slices
Speed	65 MHz	77 MHz	72 MHz
Target Device T1 Deframer	Virtex XCV200-6	Virtex-E XCV200E-8	Spartan-II XC2S150-6
Size	268 Slices	268 Slices	268 Slices
Speed	48 MHz	58 MHz	54 MHz

Obtainable without stringent place and route constraints (using effort level 2 for Place and Route).

Ordering information

Part number	Product Description	Supported Devices
DO-DI-T1E1FRAM	T1E1 Framer	Virtex, Virtex-E, Spartan-II
DO-DI-T1DEFRAM	T1 Deframer	Virtex, Virtex-E, Spartan-II

Please contact your local Xilinx Sales Office for pricing information or to place an order. Xilinx T1/E1 LogiCORE products are provided as a single-use license under the Xilinx Core Project License agreement.