There is no pin compatibility between these families. When converting XPLA2 designs to XPLA3 devices, all I/O pins will have to be re-assigned.

XPLA3 devices contain many additional architectural features not present in the other XPLA families which allow for more efficient utilization and sharing of product terms that, in most cases, reduce the number of required product terms in a function block. Features such as fold-back NANDs, input registers, hardware clock enables, and a variable function multiplexer allow for equations to be synthesized to the device in a manner that can reduce the required product terms.

For example, input pins that were registered in the previous XPLA families required the use of a product term to route from the input pin to the register input. In the XPLA3 family of devices, there is a direct connection from the input pin to the register input that does not require the use of a product term, therefore, providing more efficient utilization of the device resources.

Since the total number of product terms available in a function block has been reduced from 112 to 48, there may be a small percentage of designs that require more product terms than available in the XPLA3 function block. These designs should be examined to see if any unnecessary features are present in the design or if the design can be optimized in any way. The design should also be examined to see if the design could be modified to take advantage of the additional features of the XPLA3 architecture. Use of fold-back NANDs, hardware latches, variable-function multiplexors and hardware clock enables can reduce the product term requirements.

For example, input pins that were registered in the previous XPLA families require the use of a product term to route from the input pin to the register input. In the XPLA3 family of devices, there is a direct connection from the input pin to the register input that does not require the use of a product term, therefore, providing more efficient utilization of the device resources.

Also, the macrocell register in XPLA3 devices can be configured as a hardware latch. In previous XPLA devices, a latch had to be implemented combinatorially in product terms. Utilizing the macrocell register as a latch can reduce the number of product terms required by the design.

Note that in the XPLA3 architecture, control terms can be used to support an asynchronous reset AND an asynchronous preset, whereas in the other XPLA families control terms could only support an asynchronous reset OR an asynchronous preset. The registers in these families did not support both an asynchronous reset and preset. Therefore, designs that required both a reset and a preset to a register were forced to make either the preset or the reset synchronous, meaning that product terms were used to force the preset or reset function in the equation for the register input. Since XPLA3 devices support both an asynchronous preset and reset, designs that require both preset and reset functions can take advantage of the preset and reset support and perhaps reduce the number of required product terms for the register input.

XPLA Original and XPLA Enhanced devices have 6 control terms per function block; XPLA2 devices have 8 control terms per function block. These control terms can be a product term or a sum term, but not a sum-of-product term. Control terms are used as asynchronous presets or resets, output enables, and product term clocks. In XPLA3 devices, 8 of the 48 product terms can be used as local control terms in each function block. In most cases, there should be no fitting issues related to control terms when converting designs from the Original or Enhanced family of devices to the XPLA3 family. If such a fitting issue does occur, please contact technical support.

Note that in the XPLA3 architecture, control terms can be used to support an asynchronous reset AND an asynchronous preset, whereas in the other XPLA families control terms could only support an asynchronous reset OR an asynchronous preset. The registers in these families did not support both an asynchronous reset and preset. Therefore, designs that required both a reset and a preset to a register were forced to make either the preset or the reset synchronous, meaning that product terms were used to force the preset or reset function in the equation for the register input. Since XPLA3 devices support both an asynchronous preset and reset, designs that require both preset and reset functions can take advantage of the preset and reset support and perhaps reduce the number of required product terms for the register input.

The XPLA3 architecture supports a single product term clock per macrocell as well as 4 local control terms that can be used as clocks. The XPLA Enhanced and XPLA2 families only support 2 local control terms per function block that could be used as product term clocks. Therefore, the XPLA3 architecture has a much more flexible means of implementing control terms as clocks which will aid the design conversion process.

Note that in the XPLA3 device architecture one local control term can be routed to a universal control term available to all function blocks. The use of the universal control term structure means that product terms aren’t required in all function blocks to generate a common control term and can reduce the number of product terms required in the older families of devices which aids the fitting process in XPLA3 devices.

XPLA Original and Enhanced families of devices provide dedicated inputs that can be used as general inputs to the device or as global clocks. The same pins exist for XPLA3 devices when a common package exists across families. These pins are directly connected to a low-skew, global clock network. There is a direct correlation from the global clock resources in the XPLA Original, Enhanced, and XPLA3 families of devices, therefore there should be no fitting issues associated with the global clocks.

XPLA2 devices also provides global clock inputs, however, these pins can not be used as general inputs to the device. However, when converting an XPLA2 design to an XPLA3 design, the global clocks in an XPLA2 device can be implemented in the same manner in XPLA3 devices. There is no pin compatibility between these families, therefore the pin-out of the XPLA3 design should be assigned such that the global clocks in the XPLA2 design are assigned to the global clock pins of the XPLA3 device. The timing for these clocks may vary, therefore the device timing should be verified.

In XPLA Original devices, the output of the product terms used to generate a product term clock is routed to one of the global clock networks through the output buffer associated with either CK1, CK2, or CK3 global clock pins. (Note that CK0 was input-only and therefore could only be used as a global clock from an external source). Since the output of the product terms connects to the global clock network through the output buffer associated with these pins, the clock signal is output on the pin. In most cases, the product term clocks used in these devices can be directly implemented in XPLA3 devices and should not cause any fitting issues.

XPLA Enhanced devices allow for clocks to be generated from product terms. If the clock is just needed within the function block, it is implemented as a local control term. Up to two local control terms can be used as clocks within the function block. If the product term clock is needed throughout the device, the output of the product terms used to generate the clock is routed to one of the global clock networks through the output buffer associated with either CK1, CK2, or CK3 global clock pins. (Note that CK0 was input-only and therefore could only be used as a global clock from an external source). Since the output of the product terms connects to the global clock network through the output buffer associated with these pins, the clock signal is output on the pin. In most cases, the product term clocks used in these devices can be directly implemented in XPLA3 devices and should not cause any fitting issues.

XPLA2 devices implements product term clocks as control terms in each function block. Two of the eight control terms in each function block can be used as clocks in the function block.

In XPLA3 devices, clocks generated from product terms will be implemented in a function block as a local control term. Up to 4 local control terms can be used as product term clocks within the function block. If the product term clock is needed throughout the device, the local control term will be routed to the universal control term network and provide a universal clock to all function blocks. Since the output of the product term can be routed to the entire device without using the output buffer of a particular pin, the product-term clock will not be output on the pin. If the system design was utilizing the fact that this clock was output on a pin in the XPLA Original or Enhanced device, this output must be defined in the XPLA3 device and assigned to the proper pin. The timing may also be slightly different for the universal clock versus the global clock network used in the XPLA Original or Enhanced device and should be verified.

In XPLA Original and Enhanced devices, the output of the product terms used to generate a product term clock is routed to one of the global clock networks through the output buffer associated with either CK1, CK2, or CK3 global clock pins. (Note that CK0 was input-only and therefore could only be used as a global clock from an external source). Since the output of the product terms connects to the global clock network through the output buffer associated with these pins, the clock signal is output on the pin.

In XPLA3 devices, clocks generated from product terms will be implemented in a function block as a local control term. If the product term clock is needed throughout the device, the local control term will be routed to the universal control term network and provide a universal clock to all function blocks. Since the output of the product term can be routed to the entire device without using the output buffer of a particular pin, the product-term clock will not be output on the pin. If the system design was utilizing the fact that this clock was output on a pin in the XPLA Original or Enhanced device, this output must be defined in the XPLA3 device and assigned to the proper pin. The timing may also be slightly different for the universal clock versus the global clock network used in the XPLA Original or Enhanced device and should be verified.

To control the output slew rate of individual signals, lines can be added to the User Constraints File (UCF) as follows for each signal:

NET net_name SLOW;

or

NET net_name FAST;

XPLA Original and Enhanced families of devices provide dedicated inputs that can be used as general inputs to the device or as global clocks. The same pins exist for XPLA3 devices when a common package exists across families. These pins are directly connected to a low-skew, global clock network. There is a direct correlation from the global clock resources in the XPLA Original, Enhanced, and XPLA3 families of devices, however, the timing delays for the global clock networks may vary across these families.

XPLA2 devices also provide global clock inputs, however, these pins can not be used as general inputs to the device. However, when converting an XPLA2 design to an XPLA3 design, the global clocks in an XPLA2 device can be implemented in the same manner in XPLA3 devices. There is no pin compatibility between these families, therefore the pin-out of the XPLA3 design should be assigned such that the global clocks in the XPLA2 design are assigned to the global clock pins of the XPLA3 device. Again, the timing for these clocks may vary, therefore, the device timing should be verified.

In XPLA Original devices, the output of the product terms used to generate a product term clock is routed to one of the global clock networks through the output buffer associated with either CK1, CK2, or CK3 global clock pins. (Note that CK0 was input-only and therefore could only be used as a global clock from an external source). Since the output of the product terms connects to the global clock network through the output buffer associated with these pins, the clock signal is output on the pin.

XPLA Enhanced devices allow clocks to be generated from product terms. If the clock is just needed within the function block, it is implemented as a local control term. Up to two local control terms can be used as clocks within the function block. If the product term clock is needed throughout the device, the output of the product terms used to generate the clock is routed to one of the global clock networks through the output buffer associated with either CK1, CK2, or CK3 global clock pins. (Note that CK0 is input-only and therefore can only be used as a global clock from an external source).

XPLA2 devices implement product term clocks as control terms in each function block. Two of the eight control terms in each function block can be used as clocks in the function block.

If the product term clock utilizes the Universal Control Term network, an additional timing adder of t_UDA is incurred. This timing of the Universal Control Term network can vary from the timing of the global clock network used in the older XPLA devices and therefore should be very carefully examined and verified.

The table below illustrates the supported JTAG functions for all XPLA Original, XPLA Enhanced, XPLA2 and XPLA3 families.

The option to use or not use JTAG pins as general purpose I/O is software selectable in WebPACK Project Navigator, under the Implement Design Process Properties window, as shown below. The JTAG pins are ISP dedicated by software default. To allow the JTAG pins to be used for general purpose I/O, this option should be de-selected.

All XPLA non-volatile devices follow a similar mechanism for power up configuration. A device starting from a non-powered state monitors the V_CC value for a sufficient voltage for operation. This minimum value is referred to as the upper threshold voltage. As V_CC rises from a non-powered state, the outputs are held in a 3-state condition. Transition across the upper threshold voltage results in the part performing a self-configuration and after configuration the device releases the 3-state outputs and begins normal operation.

The device continuously monitors V_CC for adequate operating voltage. During power down, V_CC will pass through the upper threshold and will then pass through a lower voltage threshold. The lower voltage threshold has been identified as the lowest voltage that the part will operate at (please note that devices are not characterized nor guaranteed at this voltage). As the voltage transitions downward through this threshold, all I/Os are forced into a 3-state condition.

If a device passes upward through both the lower threshold and the upper threshold, all registers in the CPLD are reset to their initial operating state. For XPLA Original devices, all registers are reset. For XPLA3 devices, the default condition is reset, however a designer may elect to have the Power On Reset signal perform a preset for designated registers.

If a device is operating at nominal V_CC, and the V_CC value drops below the upper threshold and returns to nominal, no reset will occur. If V_CC drops below the lower threshold (for any period of time) and returns to nominal V_CC, a reset will occur.

Refer to the three tables below for actual voltage levels for different device families.

When interfacing to CMOS devices, it is preferable to use rail to rail drivers to decrease total power consumption in the system. Because of the increase of power consumption of an input buffer when in the linear region, a signal input should stay as close to the voltage rail (of the device being driven) as possible to decrease total power. Accordingly, transitions from high to low or vice versa should be accomplished in as rapid a manner as possible. Additionally, many CMOS signal lines are terminated by pull up resistors. If the output signal driving this line is less than V_CC, then current will flow into the output, thereby increasing total system power consumption. Refer to XAPP329 ’Understanding True CMOS Outputs’ for additional details.

In the same regard that CMOS inputs should be driven with rail to rail outputs, consideration should be given to systems that employ multiple voltage levels for powering logic devices. In the case of mixed voltage (3.3V driving 5V), under driving a 5 volt device input can cause the 5V device to consume significantly more power. Refer to the below table for an example of typical power consumption for a single pin in a 5V CMOS static environment. This data was taken from a 5032C device being driven at varied input levels. Note that this is typical for this device; other CMOS devices may be more or less sensitive to input drive voltages. Designers should evaluate this effect on their systems.

In addition to increasing the voltage of the XPLA3 device, a reduction in V_CC of the 5V components will result in less sensitivity to the low drive voltage that the XPLA3 CPLDs provide. A reduction in as little as 0.25V (to 4.75V) may compensate for the lowered drive voltage and result in no (or very little) system power increase. However, the reduced 5V rail may have timing impact on the 5V components, resulting in slightly slower operating speeds. Therefore system timing should be carefully examined.

In addition to running XPLA3 devices at a higher V_CC, external resistors may be used to pull the outputs up to 5V. It is recommended that the slew rate control be set to ‘Fast’ (default state) to minimize power consumption due to transition time ‘shoot through’.

When used with external pull-up resistors, the XPLA3 output will swing quickly to the XPLA3 V_CC rail and the external resistor network will raise V_OH to 5V according to the external time constant of the node. Because system power will now be wasted through the pull-up resistor when the output is driven low, the designer is encouraged to carefully select the value of the resistor used to pull up the signal line. This technique is best used on signal lines that are primarily high during operation, such as reset or interrupt lines.

In many instances, signals may be programmed to accept either a high or low input as the active condition. A careful analysis of the amount of time spent in the active vs. inactive state may provide insight to a way to decrease system operating power. For an example, consider a processor has a programmable sensitivity (high or low) to an interrupt signal, and an interrupt that only occurs 2% of the time during normal operation. It would be best (from a low power perspective) to have the interrupt be programmed as active high. This would allow the CPLD to maintain the input to the processor as normally low, and would only drive the input high for 2% of the operating time. This will soften the impact of mixed voltage interfacing. For additional power saving techniques, refer to XAPP346 "Low Power Tips for CoolRunner CPLD Designs".

The following devices do not have internal termination on the I/O pins:

XCR3032
XCR5032
XCR3032C
XCR5032C
XCR22LV10
XCR22V10

XCR3064
XCR5064
XCR3128
XCR5128
XCR5064C
XCR5128C
XCR3032A
XCR3064A
XCR3128A
XCR3320
XCR3960