Category: General
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Why are these families being discontinued? |
The XPLA Original, XPLA Enhanced, XPLA2 and 22V10 families were acquired from Philips Semiconductors in August 1999. At that time Xilinx initiated agreements with these new wafer foundries which
supported the availability of these older XPLA products. Unfortunately, based on recent conditions, Xilinx is unable to formally extend these agreements. |
Why doesn’t Xilinx transfer these products to a Xilinx controlled fabrication facility? |
The fabrication of these families involves unique process steps and design rules. To transfer these families would involve a full redesign of the products, which would take a longer time to
achieve than Xilinx will have product to ship. As this would mean a period of non-delivery to the customer base, the decision was made to offer last time buy quantities to the customer base in as timely a manner as possible. |
Will the CoolRunner XPLA3 family be affected? |
No, the CoolRunner XPLA3 family is being fabricated at a strategic supplier location, so this family is not affected by this discontinuation. |
Does this affect the XC9500 or XC9500XL product families? |
No, the XC9500 and XC9500XL product families are being fabricated at a strategic supplier location, so these families will not be affected by this discontinuation. |
How long do I have to order these discontinued devices? |
The last time buy date for all products listed in PDN2000-07 is April 27, 2001. |
How long will you continue to ship these discontinued devices? |
The last time ship date for all products listed in PDN2000-07 is December 28, 2001. |
Will I be able to purchase an unlimited quantity of these discontinued devices during the last time buy period? |
While no supplier can guarantee unlimited supply, we foresee no capacity issues in shipping last time buy quantities to the customer base. |
What is the current leadtime for the discontinued XPLA devices? |
The current leadtime for these devices varies from stock to 6 weeks. We do not anticipate any lengthening of leadtimes during the discontinuation process. |
Where can I purchase these XPLA devices? |
You can purchase these devices through your normal supply channel, either direct from Xilinx or through a Xilinx authorized distributor. |
Who do I contact if I have questions about this discontinuation? |
For technical questions please contact Xilinx Technical Support. For other questions please contact your local Xilinx
sales representative. |
Category: Device Resources
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Will a 22V10 design fit into a XPLA3 32 macrocell device? |
The architecture of the 22V10 is dramatically different from the XPLA CPLD architectures. No device fitting issues are anticipated, however if a fitting issue occurs, please contact technical support for assistance.
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Is there a difference in the number of macrocells per function block with CoolRunner XPLA3 devices and the XPLA Original and Enhanced families?
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The Original, Enhanced, and XPLA3 families all contain the same number of macrocells per function block. Therefore, there are no fitting issues associated with these device resources.
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Is there a difference in the number of available I/O pins between CoolRunner XPLA3 devices and the XPLA Original and Enhanced families?
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When a common package is available across device families, the pin-out is consistent and the same number of I/O pins are available. Therefore, there are no fitting issues associated with these device resources.
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Is there a difference in the number of macrocells per function block with CoolRunner XPLA3 devices and the XPLA2 family?
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The XPLA2 family of CPLDs do not directly correlate across macrocell counts with the XPLA3 family. XPLA2 devices provide 20 macrocells per function block, XPLA3 devices provide 16. When converting XPLA2 designs to XPLA3
devices, the entire design structure may need to re-partitioned across function blocks.
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Is there a difference in the number of available I/O pins between CoolRunner XPLA3 devices and the XPLA2 family?
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There is no pin compatibility between these families. When converting XPLA2 designs to XPLA3 devices, all I/O pins will have to be re-assigned.
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Are there more or less product terms in XPLA3 devices?
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CoolRunner XPLA3 devices employ a full PLA as the product term array whereas the XPLA Original and XPLA Enhanced families employ a PAL + PLA structure. In the Original and Enhanced families, each macrocell in a function
block has 5 dedicated product terms from the PAL array. Each function block also contains a PLA with 32 product terms which can be used as needed by one or all of the 16 macrocells in the function block. Therefore, the total number of product terms
available in a function block is (5*16)+32 = 112.
The XPLA2 family of devices also employs a PAL+PLA structure with 4 dedicated product terms per macrocell and 32 product terms in the PLA. The total number of product terms available in each function block is the same
as in the Original and Enhanced families at (4*20)+32 = 112.
Function blocks in XPLA3 devices contain a pure PLA product term structure, which contain 48 product terms for use by all 16 macrocells in the function block. However, XPLA3 devices contain many additional architectural
features not present in the other XPLA families which allow for more efficient utilization and sharing of product terms that, in most cases, reduce the number of required product terms in a function block. Features such as fold-back NANDs, input
registers, hardware clock enables, and a variable function multiplexer allow for equations to be synthesized to the device in a manner that can reduce the required product terms.
For example, input pins that were registered in the previous XPLA families required the use of a product term to route from the input pin to the register input. In the XPLA3 family of devices, there is a direct connection
from the input pin to the register input that does not require the use of a product term, therefore, providing more efficient utilization of the device resources.
Also, the macrocell register in XPLA3 devices can be configured as a hardware latch. In previous XPLA devices, a latch had to be implemented combinatorially in product terms. Utilizing the macrocell register as a latch
can reduce the number of product terms required by the design.
However, since the total number of product terms available in a function block has been reduced from 112 to 48, there may be a small percentage of designs that require more product terms than available in the XPLA3
function block. These designs should be examined to see if any unnecessary features are present in the design or if the design can be optimized in any way. The design should be examined to see if the design could be modified to take advantage of
the additional features of the XPLA3 architecture and thus reduce the product term requirements. If the number of product terms is only exceeded in specific function blocks, the timing and functionality of the design should examined to see if equations
could be broken into internal nodes. These internal nodes could then be placed into other function blocks and ease the product term requirement of the problematic function blocks.
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What new features exist in XPLA3 devices which may reduce the number of product terms required by my design?
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XPLA3 devices contain many additional architectural features not present in the other XPLA families which allow for more efficient utilization and sharing of product terms that, in most cases, reduce the number of required
product terms in a function block. Features such as fold-back NANDs, input registers, hardware clock enables, and a variable function multiplexer allow for equations to be synthesized to the device in a manner that can reduce the required product
terms.
For example, input pins that were registered in the previous XPLA families required the use of a product term to route from the input pin to the register input. In the XPLA3 family of devices, there is a direct connection from the input pin to
the register input that does not require the use of a product term, therefore, providing more efficient utilization of the device resources.
Also, the macrocell register in XPLA3 devices can be configured as a hardware latch. In previous XPLA devices, a latch had to be implemented combinatorially in product terms. Utilizing the macrocell register as a latch
can reduce the number of product terms required by the design.
The use of fold-back NANDs in XPLA3 devices can reduce the number of product terms required by certain equations. Fold-back NANDs were not available in previous XPLA families. If a design requires more product terms than
available in an XPLA3 device, the designer should enable the use of fold-back NANDs and re-implement the design. Fold-back NANDs are disabled by default, but can be enabled by editing the Implement Design Process Properties and selecting
to Use Foldback NANDs as shown below:
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The design that I’m converting from a previous XPLA family requires more product terms than available in the XPLA3 device. What should I do? |
Since the total number of product terms available in a function block has been reduced from 112 to 48, there may be a small percentage of designs that require more product terms than available in the XPLA3 function block. These designs should
be examined to see if any unnecessary features are present in the design or if the design can be optimized in any way. The design should also be examined to see if the design could be modified to take advantage of the additional features of the
XPLA3 architecture. Use of fold-back NANDs, hardware latches, variable-function multiplexors and hardware clock enables can reduce the product term requirements.
For example, input pins that were registered in the previous XPLA families require the use of a product term to route from the input pin to the register input. In the XPLA3 family of devices, there is a direct connection from the input pin to
the register input that does not require the use of a product term, therefore, providing more efficient utilization of the device resources.
Also, the macrocell register in XPLA3 devices can be configured as a hardware latch. In previous XPLA devices, a latch had to be implemented combinatorially in product terms. Utilizing the macrocell register as a latch can reduce the number of
product terms required by the design.
Note that in the XPLA3 architecture, control terms can be used to support an asynchronous reset AND an asynchronous preset, whereas in the other XPLA families control terms could only support an asynchronous reset OR an asynchronous preset. The
registers in these families did not support both an asynchronous reset and preset. Therefore, designs that required both a reset and a preset to a register were forced to make either the preset or the reset synchronous, meaning that product terms
were used to force the preset or reset function in the equation for the register input. Since XPLA3 devices support both an asynchronous preset and reset, designs that require both preset and reset functions can take advantage of the preset and
reset support and perhaps reduce the number of required product terms for the register input.
The use of fold-back NANDs in XPLA3 devices can reduce the number of product terms required by certain equations. Fold-back NANDs were not available in previous XPLA families. If a design requires more product terms than
available in an XPLA3 device, the designer should enable the use of fold-back NANDs and re-implement the design. Fold-back NANDs are disabled by default, but can be enabled by editing the Implement Design Process Properties and selecting
to Use Foldback NANDs as shown below:
![Process Properties](images/device_resource1.gif)
If the number of product terms is only exceeded in specific function blocks, the timing and functionality of the design should examined to see if equations could be broken into internal nodes. These internal nodes could
then be placed into other function blocks and ease the product term requirement of the problematic function blocks.
If the design will still not fit, please contact technical support for additional help in converting the design. Some designs may require migration to the next higher macrocell count device. Additionally, the reduced
number of product terms in XPLA3 devices may cause pin retention issues when converting from XPLA Original to XPLA3 CPLDs.
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How is the use of fold-back NANDs enabled? |
The use of fold-back NANDs in XPLA3 devices can reduce the number of product terms required by certain equations. Fold-back NANDs were not available in previous XPLA families. If a design requires more product terms than
available in an XPLA3 device, the designer should enable the use of fold-back NANDs and re-implement the design. Fold-back NANDs are disabled by default, but can be enabled by editing the Implement Design Process Properties and selecting
to Use Foldback NANDs as shown below:
![Process Properties](images/device_resource1.gif)
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Are there any differences in the fan-in to a function block between previous XPLA devices and CoolRunner XPLA3 devices?
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All XPLA CPLD families provide the same number of fan-in to each function block, therefore there should not be any fitting issues associated with this device resource. Please contact technical support if a design does
not successfully convert to a XPLA3 design due to function block fan-in.
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Will the control terms be implemented differently in CoolRunner XPLA3 devices than they were in previous XPLA devices? |
XPLA Original and XPLA Enhanced devices have 6 control terms per function block; XPLA2 devices have 8 control terms per function block. These control terms can be a product term or a sum term, but not a sum-of-product term. Control terms are used
as asynchronous presets or resets, output enables, and product term clocks. In XPLA3 devices, 8 of the 48 product terms can be used as local control terms in each function block. In most cases, there should be no fitting issues related to control
terms when converting designs from the Original or Enhanced family of devices to the XPLA3 family. If such a fitting issue does occur, please contact technical support.
Note that in the XPLA3 architecture, control terms can be used to support an asynchronous reset AND an asynchronous preset, whereas in the other XPLA families control terms could only support an asynchronous reset OR an asynchronous preset. The
registers in these families did not support both an asynchronous reset and preset. Therefore, designs that required both a reset and a preset to a register were forced to make either the preset or the reset synchronous, meaning that product terms
were used to force the preset or reset function in the equation for the register input. Since XPLA3 devices support both an asynchronous preset and reset, designs that require both preset and reset functions can take advantage of the preset and
reset support and perhaps reduce the number of required product terms for the register input.
The XPLA3 architecture supports a single product term clock per macrocell as well as 4 local control terms that can be used as clocks. The XPLA Enhanced and XPLA2 families only support 2 local control terms per function block that could be used
as product term clocks. Therefore, the XPLA3 architecture has a much more flexible means of implementing control terms as clocks which will aid the design conversion process.
Note that in the XPLA3 device architecture one local control term can be routed to a universal control term available to all function blocks. The use of the universal control term structure means that product terms aren’t required in all function
blocks to generate a common control term and can reduce the number of product terms required in the older families of devices which aids the fitting process in XPLA3 devices.
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Are both asynchronous reset and preset supported in XPLA3 devices? How is this implemented?
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Note that in the XPLA3 architecture, control terms can be used to support an asynchronous reset AND an asynchronous preset, whereas in the other XPLA families control terms could only support an asynchronous reset OR an
asynchronous preset. The registers in these families did not support both an asynchronous reset and preset. Therefore, designs that required both a reset and a preset to a register were forced to make either the preset or the reset synchronous, meaning
that product terms were used to force the preset or reset function in the equation for the register input. Since XPLA3 devices support both an asynchronous preset and reset, designs that require both preset and reset functions can take advantage
of the preset and reset support and perhaps reduce the number of required product terms for the register input.
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My design utilized the Global 3-state Input available in previous XPLA devices. How will this signal be implemented in CoolRunner XPLA3 devices?
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XPLA Original, XPLA Enhanced, and XPLA2 families allow one of the dedicated input pins to be used as a Global 3-state. When this signal is asserted, the entire device will 3-state for bed
of nails Automatic Test Equipment environments. XPLA3 devices do not need this pin since a Universal Control Term can be used to globally 3-state all outputs as required. For details on this subject, see "XAPP334:
Utilizing XPLA3 Universal Control Terms". Since this signal is generated from a product-term, both negative and positive assertions of the external GTS input can be supported. The output enable signal is
active-high within XPLA3 devices. Note that the timing may vary, therefore, device timing should be verified.
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My design utilized the Global Reset Input available in XPLA2 devices. How will this signal be implemented in XPLA3 devices?
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The XPLA2 family supports a global reset input. When this signal is asserted, all registers within the device are reset. This signal is active low. CoolRunner
XPLA3 devices do not need this pin since a Universal Control Term can be used to reset all device registers as required. For details on this subject, see "XAPP334: Utilizing
XPLA3 Universal Control Terms". Since this signal is generated from a product-term, both negative and positive assertions of the external global reset input can be supported. The universal reset is active-high
within XPLA3 devices. Note that the timing may vary, therefore device timing should be verified.
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Do XPLA3 devices support global clocks? Will there be any fitting issues associated with global clocks when I convert my design? |
XPLA Original and Enhanced families of devices provide dedicated inputs that can be used as general inputs to the device or as global clocks. The same pins exist for XPLA3 devices when a common package exists across families. These pins are directly
connected to a low-skew, global clock network. There is a direct correlation from the global clock resources in the XPLA Original, Enhanced, and XPLA3 families of devices, therefore there should be no fitting issues associated with the global clocks.
XPLA2 devices also provides global clock inputs, however, these pins can not be used as general inputs to the device. However, when converting an XPLA2 design to an XPLA3 design, the global clocks in an XPLA2 device can be implemented in the same
manner in XPLA3 devices. There is no pin compatibility between these families, therefore the pin-out of the XPLA3 design should be assigned such that the global clocks in the XPLA2 design are assigned to the global clock pins of the XPLA3 device.
The timing for these clocks may vary, therefore the device timing should be verified.
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Do XPLA3 devices support dedicated inputs? Will there be any fitting issues associated with dedicated inputs when I convert my design
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XPLA Original and Enhanced families of devices provide dedicated inputs that can be used as general inputs to the device or as global clocks. XPLA3 devices also provide dedicated inputs that can be used as general inputs
to the device or as global clocks.
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My design utilized a Product Term Clock – how will this be implemented in a XPLA3 device?
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In XPLA Original devices, the output of the product terms used to generate a product term clock is routed to one of the global clock networks through the output buffer associated with either CK1, CK2, or CK3 global clock pins. (Note that CK0 was
input-only and therefore could only be used as a global clock from an external source). Since the output of the product terms connects to the global clock network through the output buffer associated with these pins, the clock signal is output
on the pin. In most cases, the product term clocks used in these devices can be directly implemented in XPLA3 devices and should not cause any fitting issues.
XPLA Enhanced devices allow for clocks to be generated from product terms. If the clock is just needed within the function block, it is implemented as a local control term. Up to two local control terms can be used as clocks within the function
block. If the product term clock is needed throughout the device, the output of the product terms used to generate the clock is routed to one of the global clock networks through the output buffer associated with either CK1, CK2, or CK3 global
clock pins. (Note that CK0 was input-only and therefore could only be used as a global clock from an external source). Since the output of the product terms connects to the global clock network through the output buffer associated with these pins,
the clock signal is output on the pin. In most cases, the product term clocks used in these devices can be directly implemented in XPLA3 devices and should not cause any fitting issues.
XPLA2 devices implements product term clocks as control terms in each function block. Two of the eight control terms in each function block can be used as clocks in the function block.
In XPLA3 devices, clocks generated from product terms will be implemented in a function block as a local control term. Up to 4 local control terms can be used as product term clocks within the function block. If the product term clock is needed
throughout the device, the local control term will be routed to the universal control term network and provide a universal clock to all function blocks. Since the output of the product term can be routed to the entire device without using the output
buffer of a particular pin, the product-term clock will not be output on the pin. If the system design was utilizing the fact that this clock was output on a pin in the XPLA Original or Enhanced device, this output must be defined in the XPLA3
device and assigned to the proper pin. The timing may also be slightly different for the universal clock versus the global clock network used in the XPLA Original or Enhanced device and should be verified.
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My design took advantage of the fact that product term clocks were output on global clock pins. Is this done in XPLA3 devices? If not, what should I do?
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In XPLA Original and Enhanced devices, the output of the product terms used to generate a product term clock is routed to one of the global clock networks through the output buffer associated with either CK1, CK2, or CK3 global clock pins. (Note
that CK0 was input-only and therefore could only be used as a global clock from an external source). Since the output of the product terms connects to the global clock network through the output buffer associated with these pins, the clock signal
is output on the pin.
In XPLA3 devices, clocks generated from product terms will be implemented in a function block as a local control term. If the product term clock is needed throughout the device, the local control term will be routed to the universal control term
network and provide a universal clock to all function blocks. Since the output of the product term can be routed to the entire device without using the output buffer of a particular pin, the product-term clock will not be output on the pin. If
the system design was utilizing the fact that this clock was output on a pin in the XPLA Original or Enhanced device, this output must be defined in the XPLA3 device and assigned to the proper pin. The timing may also be slightly different for
the universal clock versus the global clock network used in the XPLA Original or Enhanced device and should be verified.
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Will I have enough clocking resources in a XPLA3 device?
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Note that XPLA3 devices support significantly more clocking resources per macrocell than ever available before in other XPLA CPLD families. In addition to the global and universal clocks, each macrocell can have a single
product-term clock or can be clocked from up to 4 local control terms in the function block. The XPLA Enhanced and XPLA2 families only support 2 local control terms per function block that can be used as product term clocks. Therefore, the XPLA3
architecture has a much more flexible means of implementing control terms as clocks which will aid the design conversion process.
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Category: Device Timing
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Will I have timing problems when converting a design from another XPLA CPLD family to XPLA3 devices?
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Whenever a design is converted from the XPLA Original, XPLA Enhanced, or XPLA2 families to a XPLA3 device, the timing should be verified by carefully examining the timing report to insure that the system timing requirements
have been met. In most cases, the XPLA3 family offers a faster speed grade than was previously available. Even within the same speed grade, some paths are slightly faster than in the previous families. Please refer to the white paper, WP105,
"XPLA3 CoolRunner CPLD Architecture Overview" and white paper, WP122, "Using the CoolRunner XPLA3 Timing Model"
for more details about XPLA3 device timing. While most designs should convert to the XPLA3 family with improved timing, there may be some designs where timing issues exist. In these cases, please contact technical support for help in evaluating the
timing issue.
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Will there be any timing issues if I convert a 22V10 design to a CoolRunner XPLA3 32-macrocell design?
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The architecture of the 22V10 is dramatically different from the XPLA CPLD architectures. No device timing issues are anticipated, however if a timing issue occurs, please contact technical support for assistance.
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How does the timing differ in XPLA3 since the Product Term array is a PLA and the XPLA Original, Enhanced and XPLA 2 families used a PAL and a PLA Product Term Array?
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CoolRunner XPLA3 devices employ a full PLA as the product term array whereas the XPLA Original and XPLA Enhanced families employ a PAL + PLA structure. In the Original and Enhanced families, each macrocell in a function
block has 5 dedicated product terms from the PAL array. Each function block also contains a PLA with 32 product terms, which can be used as needed by one or all of the 16 macrocells in the function block. The XPLA2 family of devices also employs
a PAL+PLA structure with 4 dedicated product terms per macrocell and 32 product terms in the PLA.
For XPLA Original and XPLA2 devices, if the macrocell equation only utilized the product terms in the PAL (i.e. the dedicated product terms for the macrocell), then the delay through the array was simply tPD_PAL.
If additional product terms from the PLA were required (either 1 or all 32) then the delay through the array was tPD_PLA which typically was ~2 ns greater than tPD_PAL . The setup time for registers in the macrocell also
follow this structure in that the setup time for the register is tPD_PAL if the input equation only requires PAL product terms and is tPD_PLA if the input equation requires PAL and PLA product terms.
Function blocks in XPLA3 devices contain a pure PLA product term structure, which contain 48 product terms for use by all 16 macrocells in the function block. Each macrocell has a direct connection from one product
term which bypasses the OR function and provides a faster timing path through the array. When the macrocell equation uses a single product term, the delay through the array is simply tPD1. If 2 up to 48 product terms are required, the
delay through the array is then tPD2. The difference in timing between tPD1 and tPD2 vary across speed grades. The setup time for macrocell registers follows this same pattern.
The timing report should be carefully examined to ensure that the system timing requirements have been met. Even within the same speed grade, the path through the product term array is slightly faster than in the previous
families. However, timing issues may occur through the product term array; in these cases please contact technical support.
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What timing advantage do the Input Registers in XPLA3 devices provide? |
The XPLA3 architecture supports a direct connection from an I/O pin to the input of the macrocell register, bypassing the product term array. This provides a fast connection from the pin to the register, reducing the required
setup time on the signal to tFIN. This feature is not available on the XPLA Original, XPLA Enhanced, and XPLA2 families. When designs are converted from these previous families to an XPLA3 device, signals that are directly registered from
the pin will now be implemented using the input register and have a lower setup time requirement. The software will do this automatically when fitting a design. Designers should again analyze the timing report and verify that the timing of the XPLA3
device meets all system requirements since the input setup requirement will be less than in the previous device implementation.
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How do I use the Input Registers?
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When the design is fit into an XPLA3 device, the software will automatically route signals that are directly registered from the pin to the macrocell register, utilizing the fast input path to the macrocell register. Therefore,
the designer does not need to do anything to take advantage of this architectural feature.
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Is the Clock-to-Output Timing (tCO) faster and how will the Slow Slew Rate property help?
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In most cases, XPLA3 devices have a slightly faster clock-to-output delay than available in previous XPLA families. The timing report for the XPLA3 device should be reviewed to determine if the faster tCO still
meets system hold-time requirements for devices that interface to the XPLA3 device. If necessary, the output buffer can be configured to have a slow slew rate which will slow down the rise time of the output signal. This can be done for all outputs
of the device by editing the Implement Design Process Properties and setting Output Slew Rate to Slow as shown below:
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How is the Slow Slew Rate property applied to individual signals?
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To control the output slew rate of individual signals, lines can be added to the User Constraints File (UCF) as follows for each signal:
NET net_name SLOW;
or
NET net_name FAST;
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How will the use of Fold-back NANDs affect the timing of my design?
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XPLA3 devices contain 8 fold-back NANDs in each function block to provide more efficient synthesis of equations and utilization of product terms. However, there is an additional delay of tLOGI3 associated with
this feature. While the fold-back NANDs can reduce the number of product terms required by an equation, in some cases, the additional delay incurred by the fold-back NANDs may cause the design to not meet its timing requirements. The timing report
should be carefully analyzed to determine if equations utilizing fold-back NANDs are within the required timing specification.
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Will the software automatically implement Fold-back NANDs in my design?
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No, fold-back NANDs are disabled by default, therefore, the additional delay incurred by fold-back NANDs is only an issue if fold-back NANDs have been enabled to reduce the number of product terms required by the design.
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How can the use of Fold-back NANDs be disabled?
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In cases where fold-back NANDs have been enabled and the delay incurred by the fold-back NAND causes timing issues, the use of fold-back NANDs can be disabled by editing the Implement Design Process Properties and de-selecting
to Use Foldback NANDs as shown below:
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How is the Control Term structure different in XPLA3 devices and will this affect the timing of my design? |
XPLA Original and XPLA Enhanced devices provide 6 control terms per function block, and the XPLA2 family provides 8 control terms per function block. These control terms can be a product term or a sum term, but not a sum-of-product
term. Control terms are used as asynchronous presets or resets, output enables, and product term clocks. In XPLA3 devices, 8 of the 48 product terms can be used as local control terms in each function block. In most cases, there should be no significant
change in the timing related to control terms when converting designs from the original or enhanced family of devices to the XPLA3 family. However, the timing report should be analyzed to insure that all timing requirements have been met.
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How is the Universal Control Term used and is there a timing delay associated with this? |
Note that in the XPLA3 device architecture, one local control term can be routed to a Universal Control Term available to all function blocks. The use of the Universal Control Term structure incurs a timing delay of tUDA
which varies in magnitude across speed grades. The timing report should again be carefully examined to determine if the Universal Control Term timing adder incurred on Universal Control Terms still allows the design to meet system timing requirements.
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My design utilized the Global 3-state Input, which is no longer available on XPLA3 devices. How will this signal be implemented and what affect will this have on timing?
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XPLA Original, XPLA Enhanced, and XPLA2 families allow one of the dedicated input pins to be used as a Global 3-state. When this signal is asserted, the entire device would 3-state for
bed of nails Automatic Test Equipment environments. XPLA3 devices do not need this pin since a Universal Control Term can be used to perform global 3-state as required. However, use of a Universal Control Term incurs an additional timing delay of
tUDA, therefore, the timing report must be analyzed to verify that the device timing still is within the system timing specifications.
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My design utilized the Global Reset Input, which is no longer available on XPLA3 devices. How will this signal be implemented and what affect will this have on timing?
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The XPLA2 family of devices supports a global reset input. When this signal is asserted, all registers within the device are reset. XPLA3 devices do not need this pin since a Universal Control Term can be used to reset
registers as required. However, use of a Universal Control Term incurs an additional timing delay of tUDA, therefore, the timing report must be analyzed to verify that the device timing still is within the system timing specifications.
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Will there be timing issues associated with global clocks?
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XPLA Original and Enhanced families of devices provide dedicated inputs that can be used as general inputs to the device or as global clocks. The same pins exist for XPLA3 devices when a common package exists across families. These pins are directly
connected to a low-skew, global clock network. There is a direct correlation from the global clock resources in the XPLA Original, Enhanced, and XPLA3 families of devices, however, the timing delays for the global clock networks may vary across
these families.
XPLA2 devices also provide global clock inputs, however, these pins can not be used as general inputs to the device. However, when converting an XPLA2 design to an XPLA3 design, the global clocks in an XPLA2 device can be implemented in the same
manner in XPLA3 devices. There is no pin compatibility between these families, therefore the pin-out of the XPLA3 design should be assigned such that the global clocks in the XPLA2 design are assigned to the global clock pins of the XPLA3 device.
Again, the timing for these clocks may vary, therefore, the device timing should be verified.
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How is the delay specified for global clocks in XPLA3 devices?
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XPLA3 global clocks have a delay of tGCK for the global clock buffer delay. This parameter is not individually specified in the timing parameters for the other families of devices, but is instead included in
the specification of other timing parameters. Therefore, the timing report should be carefully analyzed to determine that the XPLA3 design meets the system timing requirements.
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My design utilized a Product Term Clock – how will this be implemented in a XPLA3 device and will the timing vary?
|
In XPLA Original devices, the output of the product terms used to generate a product term clock is routed to one of the global clock networks through the output buffer associated with either CK1, CK2, or CK3 global clock pins. (Note that CK0 was
input-only and therefore could only be used as a global clock from an external source). Since the output of the product terms connects to the global clock network through the output buffer associated with these pins, the clock signal is output
on the pin.
XPLA Enhanced devices allow clocks to be generated from product terms. If the clock is just needed within the function block, it is implemented as a local control term. Up to two local control terms can be used as clocks within the function block.
If the product term clock is needed throughout the device, the output of the product terms used to generate the clock is routed to one of the global clock networks through the output buffer associated with either CK1, CK2, or CK3 global clock pins.
(Note that CK0 is input-only and therefore can only be used as a global clock from an external source).
XPLA2 devices implement product term clocks as control terms in each function block. Two of the eight control terms in each function block can be used as clocks in the function block.
In XPLA3 devices, clocks generated from product terms will be implemented in a function block as a local control term. Up to 4 local control terms can be used as product term clocks within the function block. In addition
to the local control term clocks, each macrocell has an individual, single product term that can be used as a clock for that macrocell register. If the product term clock is needed throughout the device, the local control term will be routed to
the universal control term network and provide a clock to all function blocks. When product term clocks utilize a local control term or the single product term path, the delay for that clock is tLOGI1. The timing of clocks implemented
in this manner can vary from similar clock implementations in XPLA Original, Enhanced and XPLA2 devices, therefore the timing report of the XPLA3 design should be very carefully examined.
If the product term clock utilizes the Universal Control Term network, an additional timing adder of tUDA is incurred. This timing of the Universal Control Term network can vary from the timing of the global clock network used in the
older XPLA devices and therefore should be very carefully examined and verified.
|
My design instantiates a latch. Will this be implemented in the same manner and will timing be affected? |
In XPLA Original, XPLA Enhanced, and XPLA2 families of devices, latches were supported in a combinatorial fashion. Depending on the equations required by the latch, the delay could be tPD or several tPD
factors due to feedback through the array. The macrocell registers in XPLA3 devices can be configured as a true hardware latch, thus reducing the number of product terms required by the design. The delay through the latch is specified as tLDI
which is the transparent latch delay. In most cases, the implementation of the latch in the XPLA3 device should be faster than the combinatorial implementation, however, the timing report should be carefully examined.
|
Catagory: JTAG
|
Which XPLA devices are JTAG 1149.1 compliant? |
All XPLA3 (XCR3032XL, XCR3064XL, XCR3128XL, XCR3256XL, XCR3384XL), XPLA2 (XCR3320, XCR3960) and XPLA Original (XCR3128, XCR5128) ISP devices are JTAG 1149.1 compliant. These devices may be programmed through the JTAG TAP
Pins and support specific JTAG instructions. |
Which XPLA devices are JTAG 1149.1 compatible?
|
All XPLA Enhanced (XCR3032A/C, XCR3064A, XCR3128A, XCR5032C, XCR5064C, XCR5128C) are JTAG 1149.1 compatible. These devices may be programmed through the JTAG TAP Pins and support the BYPASS and IDCODE instructions. |
Which XPLA devices do not support JTAG 1149.1?
|
The only parts that do not support JTAG 1149.1 and do not have the JTAG Tap Pins for programming are the XPLA Original (XCR3032, XCR3064, XCR5032, XCR5064) and 22V10 (XCR22LV10, XCR22V10) parts. They must be programmed
by a third party programmer. |
Which JTAG functions do the XPLA Original, XPLA Enhanced, XPLA2, and XPLA3 devices support?
|
The table below illustrates the supported JTAG functions for all XPLA Original, XPLA Enhanced, XPLA2 and XPLA3 families.
Product Family
|
Part
|
JTAG Functions Supported
|
|
22V10
22LV10
|
None
|
XPLA Original
|
XCR3032
XCR5032
XCR3064
XCR5064
|
None
|
XCR3128
XCR5128
|
BYPASS, SAMPLE/PRELOAD, EXTEST, IDCODE, and HIGHZ
|
XPLA Enhanced C
|
XCR3032C
XCR5032C
XCR5064C
XCR5128C
|
BYPASS, IDCODE
|
XPLA Enhanced A
|
XCR3032A
XCR3064A
XCR3128A
|
BYPASS, IDCODE
|
XPLA2
|
XCR3960
XCR3320
|
BYPASS, SAMPLE/PRELOAD, EXTEST, IDCODE, and HIGHZ
|
XPLA3
|
XCR3032XL
XCR3064XL
XCR3128XL
XCR3256XL
XCR3384XL
|
BYPASS, SAMPLE/PRELOAD, EXTEST, INTEST, IDCODE, and HIGHZ
|
|
What options are available for utilizing the same number of I/Os on a device that does not support JTAG ISP when transitioning to XPLA3? |
If the JTAG function of the XPLA3 device is not desired, the JTAG function of this device should be disabled in software. Since XPLA Original (XCR3032, XCR5032, XCR3064, and XCR5064) devices do not support JTAG ISP, it
provides more general purpose I/O. Therefore, it may also be necessary to turn off the JTAG port for the current pin assignment to be maintained. |
How are the JTAG port pins used as general purpose I/O pins?
|
The option to use or not use JTAG pins as general purpose I/O is software selectable in WebPACK Project Navigator, under the Implement Design Process Properties window, as shown below. The JTAG pins are ISP dedicated by software default.
To allow the JTAG pins to be used for general purpose I/O, this option should be de-selected.
![Process Properties](images/jtag1.gif)
|
What board changes are necessary for termination of JTAG pins?
|
If the JTAG function of the XPLA3 device is desired, board modifications will be necessary. Note that all JTAG pins (TDI, TDO, TCK, TMS) should be terminated to VCC to provide a stable input when not in use. For XPLA Original
or Enhanced devices that do not have internal termination, these devices may have existing external termination on the JTAG pins. If the external termination consists of pull-down resistors or connections to ground, these connections must be removed
from the JTAG pins. If the external termination consists of pull-up resistors or connections to VCC, no modification to the termination circuit is necessary. If it is desired to save board space, the external terminations can be removed when migrating
to XPLA3. XPLA3 JTAG pins (when not used as I/O) have a weak internal pull-up that is software selectable in WebPACK. This feature can be set using the two properties shown below in the Implement Design Process Properties window.
![Process Properties](images/jtag2.gif) |
What is the Port Enable pin on XPLA3?
|
XPLA3 devices allow the JTAG pins to be dual-purpose pins and used as I/O to increase the I/O count when needed. The Port Enable pin is a feature new to the CoolRunner XPLA3 family; it allows easy re-establishment of the
JTAG ISP pins if these pins have been used as general I/O after programming. For more information, refer to "XAPP343: In System Programming of XPLA3 Devices", which can be found at http://www.xilinx.com/xapp/xapp343.pdf. |
If not using the JTAG pins on an XPLA3 device, what is the Port Enable pin connected to?
|
For XPLA Original (XCR3032, XCR5032, XCR3064, and XCR5064) and 22V10 designs migrating to XPLA3, the Port Enable pin should be connected to ground: this will avoid any contention issues with using the JTAG pins for I/O. |
What are BSDL files used for?
|
BSDL files are available for devices that support JTAG and boundary scan functions. BSDL files enable designers to correctly utilize the boundary scan chain for a specific part and package combination. CoolRunner BSDL
files are available on the web for easy download and can be found at http://www.xilinx.com/support/sw_bsdl.htm#CPLD. |
Catagory: PCI
|
Which XPLA devices are PCI compliant?
|
The 3V and 5V XPLA Original devices (XCR3032, XCR5032, XCR3064, XCR5064, XCR3128, XCR5128), 5V XPLA Enhanced devices (XCR5032C, XCR5064C, XCR5128C), 3V XPLA Enhanced, XCR3032C device and the 3V XPLA2, XCR3960 device are
all PCI compliant. |
How is a device PCI compliant?
|
A device is PCI compliant by providing internal clamp diodes on the I/O pins of the part. |
Which XPLA devices are PCI compatible?
|
The 3V XPLA2, XCR3320 device, 3V XPLA Enhanced devices (XCR3032A, XCR3064A, XCR3128A), and all XPLA3 devices (XCR3032XL, XCR3064XL, XCR3128XL, XCR3256XL, and XCR3384XL) are PCI compatible. |
Which devices are not PCI compliant or compatible? |
The 3V and 5V 22V10 parts, XCR22V10 and XCR22LV10 are not PCI compliant or compatible. |
Catagory: Power-on Reset
|
How do the Power On Reset thresholds compare between XPLA Original and XPLA3 devices?
|
Power On Reset thresholds for XPLA3 devices are more stable in all respects than previous XPLA families. No migration issues should be experienced.
|
What is operation of the POR cycle? |
All XPLA non-volatile devices follow a similar mechanism for power up configuration. A device starting from a non-powered state monitors the VCC value for a sufficient voltage for operation. This minimum value is referred to as the
upper threshold voltage. As VCC rises from a non-powered state, the outputs are held in a 3-state condition. Transition across the upper threshold voltage results in the part performing a self-configuration and after configuration the
device releases the 3-state outputs and begins normal operation.
The device continuously monitors VCC for adequate operating voltage. During power down, VCC will pass through the upper threshold and will then pass through a lower voltage threshold. The lower voltage threshold has been
identified as the lowest voltage that the part will operate at (please note that devices are not characterized nor guaranteed at this voltage). As the voltage transitions downward through this threshold, all I/Os are forced into a 3-state condition.
|
Are there any differences between the POR circuits between XPLA Original and XPLA3?
|
XPLA Enhanced ‘A’ and XPLA3 devices have dual hysteresis circuits where the lower threshold is adjusted downward after initialization.
|
What happens if my VCC dips down below the normal operating VCC?
|
If a device passes upward through both the lower threshold and the upper threshold, all registers in the CPLD are reset to their initial operating state. For XPLA Original devices, all registers are reset. For XPLA3 devices, the default condition
is reset, however a designer may elect to have the Power On Reset signal perform a preset for designated registers.
If a device is operating at nominal VCC, and the VCC value drops below the upper threshold and returns to nominal, no reset will occur. If VCC drops below the lower threshold (for any period of time) and returns
to nominal VCC, a reset will occur.
Refer to the three tables below for actual voltage levels for different device families.
XPLA Original and Enhanced ‘C’
|
Upper Threshold
|
Lower Threshold Before Init
|
Lower Threshold After Init
|
Typical at 25C
|
2.40 V
|
1.95 V
|
1.95 V
|
Over Process Corners at 25C
|
1.95 – 2.85 V
|
1.55 – 2.20 V
|
1.55 – 2.20 V
|
Over Process Corners –40 to 80C
|
1.80 – 2.95 V
|
1.60 – 2.60 V
|
1.60 – 2.60 V
|
XPLA Enhanced ‘A’
|
Upper Threshold
|
Lower Threshold Before Init
|
Lower Threshold After Init
|
Typical at 25C
|
2.25 V
|
2.15 V
|
1.60 V
|
Over Process Corners at 25C
|
1.90 – 2.50 V
|
1.80 – 2.40 V
|
1.45 – 1.75 V
|
Over Process Corners –40 to 80C
|
1.75 – 2.65 V
|
1.70 – 2.55 V
|
1.20 – 1.90 V
|
XPLA3
|
Upper Threshold
|
Lower Threshold Before Init
|
Lower Threshold After Init
|
Typical at 25C
|
2.03 V
|
1.95 V
|
1.65 V
|
Over Process Corners at 25C
|
2.00 – 2.05 V
|
1.92 – 1.97 V
|
1.62 – 1.68 V
|
Over Process Corners –40 to 80C
|
1.96 – 2.08 V
|
1.88 – 2.00 V
|
1.58 – 1.71 V
|
|
Category: System Power
|
How will migrating to XPLA3 devices generally affect my system power? |
XPLA3 devices are only available in 3.3V (nominal) operation. For 3.3V systems, migration to the XPLA3 family from XPLA Original 3V devices will result in a reduction of system power consumption due to process improvements.
|
When I replace my 5V parts with XPLA3 devices, will this result in a decrease of system power?
|
Replacement of 5V XPLA Original parts with the XPLA3 devices requires a change in VCC for the socket, and may result in higher overall system power consumption if the system now has mixed VCC power
rails.
|
What issues should I be aware of when implementing CMOS devices in a mixed voltage system?
|
When interfacing to CMOS devices, it is preferable to use rail to rail drivers to decrease total power consumption in the system. Because of the increase of power consumption of an input buffer when in the linear region, a signal input should
stay as close to the voltage rail (of the device being driven) as possible to decrease total power. Accordingly, transitions from high to low or vice versa should be accomplished in as rapid a manner as possible. Additionally, many CMOS signal
lines are terminated by pull up resistors. If the output signal driving this line is less than VCC, then current will flow into the output, thereby increasing total system power consumption. Refer to XAPP329 ’Understanding True CMOS
Outputs’ for additional details.
In the same regard that CMOS inputs should be driven with rail to rail outputs, consideration should be given to systems that employ multiple voltage levels for powering logic devices. In the case of mixed voltage (3.3V driving 5V), under driving
a 5 volt device input can cause the 5V device to consume significantly more power. Refer to the below table for an example of typical power consumption for a single pin in a 5V CMOS static environment. This data was taken from a 5032C device being
driven at varied input levels. Note that this is typical for this device; other CMOS devices may be more or less sensitive to input drive voltages. Designers should evaluate this effect on their systems.
Input Pin Voltage Level
|
ICC Quiescent
|
5.0 V
|
50 uA
|
3.6 V
|
62 uA
|
3.3V
|
83 uA
|
3.0
|
107 uA
|
2.7
|
135 uA
|
|
Are there ways to reduce the problems associated with mixed voltage level CMOS interfacing?
|
XPLA3 devices have an absolute maximum Vcc level of 3.6 V. To minimize system power consumption, increase Vcc to a higher level which will in turn create a higher Voh. At a Vcc of 3.6V, there is no tolerance to noise or
power transients which may drive Vcc above the 3.6V limit. Caution is advised when approaching this upper Vcc limit. Refer to ‘Device Voltage Compatibility’ for additional information.
|
Are there any specific 5V XPLA Original parts that are replaced with XPLA3 devices and will only have a minor impact on the system?
|
The 5064C and 128C devices do not employ true CMOS outputs as they have non-complementary output structures. Because of the N-channel pull-up transistor in the output, the VOH output is limited to approximately
3.5V when operated at a nominal VCC of 5V. Replacement of these devices with an XPLA3 CPLD should have little or no impact on system power, especially if the XPLA3 device is powered at 3.5 volts.
|
What can I do to further reduce system power consumption?
|
In addition to increasing the voltage of the XPLA3 device, a reduction in VCC of the 5V components will result in less sensitivity to the low drive voltage that the XPLA3 CPLDs provide. A reduction in as little as 0.25V (to 4.75V) may
compensate for the lowered drive voltage and result in no (or very little) system power increase. However, the reduced 5V rail may have timing impact on the 5V components, resulting in slightly slower operating speeds. Therefore system timing should
be carefully examined.
In addition to running XPLA3 devices at a higher VCC, external resistors may be used to pull the outputs up to 5V. It is recommended that the slew rate control be set to ‘Fast’ (default state) to minimize power consumption due to transition
time ‘shoot through’.
When used with external pull-up resistors, the XPLA3 output will swing quickly to the XPLA3 VCC rail and the external resistor network will raise VOH to 5V according to the external time constant of the node. Because system
power will now be wasted through the pull-up resistor when the output is driven low, the designer is encouraged to carefully select the value of the resistor used to pull up the signal line. This technique is best used on signal lines that are
primarily high during operation, such as reset or interrupt lines.
In many instances, signals may be programmed to accept either a high or low input as the active condition. A careful analysis of the amount of time spent in the active vs. inactive state may provide insight to a way to decrease system operating
power. For an example, consider a processor has a programmable sensitivity (high or low) to an interrupt signal, and an interrupt that only occurs 2% of the time during normal operation. It would be best (from a low power perspective) to have the
interrupt be programmed as active high. This would allow the CPLD to maintain the input to the processor as normally low, and would only drive the input high for 2% of the operating time. This will soften the impact of mixed voltage interfacing.
For additional power saving techniques, refer to XAPP346 "Low Power Tips for CoolRunner CPLD Designs".
|
Category: Unused IO Termination
|
What internal termination is provided on unused I/O pins with XPLA3?
|
All XPLA3 devices have weak internal pull-up resistors available on unused I/O pins. |
How are the weak internal pull-up resistors implemented in XPLA3?
|
The internal pull-up resistor on unused I/O is selectable in WebPACK Project Navigator in the Implement Design Process Properties window as shown below. The default setting enables the implementation of pull-up
resistors on unused I/O pins. To disable the implementation of internal pull-up resistors, this box can be deselected By disabling any internal termination, the I/O pins remain in a high impedance state.
![Process Properties](images/unusedio1.gif)
|
What devices do not provide any internal termination on the I/O pins?
|
The following devices do not have internal termination on the I/O pins:
XCR3032
XCR5032
XCR3032C
XCR5032C
XCR22LV10
XCR22V10
|
What devices have internal weak pull-down resistors on unused I/O pins?
|
The following devices have internal weak pull-down resistors on unused I/O pins:
XCR3064
XCR5064
XCR3128
XCR5128
XCR5064C
XCR5128C
XCR3032A
XCR3064A
XCR3128A
XCR3320
XCR3960
|
What I/O termination design changes are necessary when migrating to XPLA3?
|
When moving designs to XPLA3 where external termination on unused I/O pins is already present on the board, no changes are necessary. The internal pull-up resistors for unused I/O pins in XPLA3 must be disabled in the
software to meet your board requirements. If additional board savings are needed, the XPLA3 internal pull-up resistors can be used with no need for external termination. |
Category: Voltage Compatibility
|
What operating voltage do XPLA3 devices require?
|
XPLA3 industrial temperature range CPLDs are 3.3V devices with an absolute maximum operating VCC of 3.6V. Commercial parts are characterized from 3.0V to 3.6V, and industrial parts are characterized from 2.7V
to 3.6V. In some cases, it is advantageous to power the XPLA3 CPLDs at voltage levels higher than nominal.
|
Do XPLA3 devices have 5V tolerant I/Os?
|
All XPLA3 CPLDs have 5V tolerant inputs only while the device is powered. They are capable of accepting an input signal being applied before VCC is established, as long as the input does not exceed the voltage
on the XPLA3 VCC pins by more than 3.6V. Once VCC is applied, the voltage on any input pin can not exceed 5V.
|
Can I implement 'hot swap' designs using XPLA3 devices?
|
All XPLA3 CPLDs have 5V tolerant inputs only while the device is powered. They are capable of accepting an input signal being applied before VCC is established, as long as the input does not exceed the voltage
on the XPLA3 VCC pins by more than 3.6V. Once VCC is applied, the voltage on any input pin can not exceed 5V.
|
Can I use XPLA3 devices to replace my XPLA Original 3.3V parts?
|
With regards to voltage compatibility, XPLA3 devices may be treated as ‘drop in’ replacements for any XPLA Original 3.3V part.
|
Can I use XPLA3 devices to replace my XPLA Original 5V parts?
|
XPLA3 devices can not ‘drop in’ to a 5V system without a change to the VCC power distribution. A small Low Drop Out (LDO) voltage regulator may be used to decrease the voltage to accommodate the XPLA3 power
requirements, while other devices on the board are still powered from 5V.
|
What voltage tolerance problems should I look out for when replacing XPLA Original devices with the XPLA3 family?
|
XPLA3 devices have 5V tolerant inputs only while the XPLA3 CPLD is powered. It is not recommended to apply a 5V signal to an XPLA3 whose VCC rail is non-powered. The output of a local Low Dropout Regulator (powered
off of the 5V rail) which provides a stepped down VCC to the XPLA3 device will lag the 5V rail rise by a small time margin. This lag time will not adversely affect the XPLA3 device if the input voltage to any of the XPLA3 inputs does not
exceed the VCC of the XPLA3 device by more than 3.6V. For instance, the XPLA3 device must have a VCC of at least 1.4V before any input pin is being driven by a 5V signal.
|
My 5064C and 5128C parts do not have outputs that swing all the way to the rail. How does the XPLA3 family compare to these parts in terms of output drive?
|
The 5064C and 5128C do not have true CMOS outputs. The output buffer structure uses an NMOS pull-up transistor, which means that the output voltage (VOH) does not drive to the rail. XPLA3 devices employ true
CMOS outputs and swing rail to rail. Although the nominal operating voltage of XPLA3 devices is 3.3V, XPLA3 CPLDs powered at 3.5V will have similar VOH levels as the 5064C and 5128C devices powered at 5V. |