Q. What new technology or process is Xilinx and UMC announcing?
UMC and Xilinx are announcing an FPGA with copper interconnect for the top two layers.

Q. What process geometry will use this technology?
The Virtex-E Extended Memory family of FPGAs is fabricated on a 0.18-micron, 6-layer metal process.

Q. Where do the performance improvements come from and what is the performance benefit?
Copper has lower resistivity, and ultimately lower resistance, than aluminum. This reduces the RC delays and resulting in increased performance. Copper will provide lower clock and signal skew and improved on-chip power distribution.

Q. On which products will Xilinx deploy this process?
The Virtex-E Extended Memory (Virtex-EM) will be the first product to deploy this process. 

Q. Will copper interconnect be used on any other Xilinx products?
Xilinx expects to deploy copper interconnect for all subsequent process migrations for high-density FPGAs. 

Q. How is Virtex-EM optimized for copper? 
We planned the chip layout to have power/ground on the top thickest metal layer and key signal lines such as clock and output routing to be on the second layer. In this way, the main benefits of copper in reducing IR drop and signal skew is realized. 

Q. Why are only the top two layers produced in copper? 
We have the base copper technology that can be extended to all layers in a straightforward manner. However, we decided to restricted to the top two layers at this time because we gain key benefits with only two layers (IR drop and signal skew), and we can utilize the main interconnect capacity within UMC for aluminum. Over time, when more of the UMC interconnect capacity is converted to copper (in terms of additional equipment and capacity) we will use all-layer copper.

Q. When will UMC be in full production with this copper process?
The Virtex-EM FPGA family will be in full production in the second half of 2000.

Q. What are the price differences between FPGAs with copper interconnect and aluminum interconnect?
Virtex-EM will not be priced higher due to using copper interconnect. Long-term, copper technology should offer economies over wafers processed with aluminum.

Q. What are the yield differences between wafers with copper interconnect and aluminum interconnect?
UMC copper based wafers are experiencing yields equivalent to aluminum-based wafers.

Q. What are the production differences between wafers with copper interconnect and aluminum interconnect? 
In aluminum processing, the aluminum is deposited using physical vapor deposition (PVD) and then etched. In damascene copper processing, the copper is deposited using electrochemical plating (ECP) and then excess copper is removed with chemical-mechanical planarization (CMP).

Q. Are there any packaging problems or challenges from the new copper process? 
An aluminum layer is applied over the top copper layer, allowing the die to be packaged with existing bonding and packaging equipment.

Q. Are there plans for future copper process changes? 
Future copper processes will integrate both copper and low-k dielectrics, for superior device performance.

Q.  How exactly are Xilinx and UMC partnering on this?
Over the past two years, Xilinx engineers have worked in close collaboration with UMC Group engineers toward the developed of the advanced copper process technology used to build the Virtex-EM family. More specifically, Xilinx develops the FPGA design and generates masks, while UMC fabricates the wafers. Xilinx performs the diagnostics tests and analysis to provide feedback to UMC. Through the development cycles, the process is optimized to maximize device performance and production yield.

Q. Is Xilinx the exclusive consumer of this UMC process?
Xilinx is the first to use this UMC process, but the process will be available to other companies.

Q. Is TSMC or other foundries currently shipping copper?
Our understanding is that TSMC has a copper process running in an R&D fab, and Charter Semiconductor Manufacturing, Ltd. is in development of a copper process.

Q.  Other vendors have announced development efforts on 0.15-micron copper processes. Where does Xilinx stand on 0.15-micron process delivery?
Xilinx is announcing the immediate availability of FPGAs manufactured in 0.18-micron copper processes. This is a result of a two-year collaborative development effort with UMC. Likewise, Xilinx and UMC have been developing 0.15-micron and other advanced processes for an extended period of time. The Xilinx policy is to announce products when they are available to our customers, not simply for development milestones.

Q. Are there any other semiconductor suppliers currently shipping copper either ES or full production?
IBM, Texas Instruments, and Motorola are have shipped either engineering samples or full production integrated circuits with copper interconnect. The Xilinx Virtex-E Extended Memory family is the first FPGA available with copper interconnect.