FOR IMMEDIATE RELEASE
XILINX LATEST FIR FILTER GENERATOR
Easy to use DSP tool combines performance and flexibility for Spartan and Virtex FPGAs SAN JOSE, Calif., AT THE DSP WORLD CONFERENCE, April 11, 2000—Xilinx, Inc. (NASDAQ: XLNX) today announced its latest high-performance LogiCORE Finite Impulse Response (FIR) Filter generator for use with its Spartan™ and Virtex™ family of FPGAs. The LogiCORE FIR Filter delivers equivalent performance at approximately 70 percent cost-savings over programmable DSPs with the flexibility and time-to-market advantages of an FPGA. As an alternative to DSP processors and ASICs, Xilinx® FPGAs are now able to address emerging high-volume markets such as wireless, digital communication systems, digital TV, high-speed DSL, cable modems, and medical imaging systems. “The addition of the DSP FIR Filter generator to our popular DSP library further demonstrates Xilinx leadership in offering complete DSP solutions,” said Babak Hedayati, director of marketing and business development for IP Solutions at Xilinx. “As a result, designers can further accelerate time-to-market delivery of DSP solutions.” The Xilinx FIR Filter is highly parameterizable supporting 2-to-256 tap impulse response, 1-to-32 bit input data/coefficient precision, and a wide range of high-performance filter features including: half-band, Hilbert transforms, and interpolated filters. An implementation methodology known as "distributed arithmetic" efficiently maps filters to the FPGA architecture. Using designer specifications, the tool automatically generates a FIR filter including netlist, VHDL/Verilog simulation models, and VHDL/Verilog instantiation code. By employing Xilinx unique Smart-IP Technology™, the generator maintains performance over the entire range of FPGA densities. This predictability, unique to Xilinx, is essential for designers incorporating entire systems on an FPGA. A Powerful Cost Competitive Solution
“The Xilinx Spartan and Virtex devices offer powerful features such as high-performance shift registers, BlockRAM™, Distributed RAM, and delay locked loop (DLL) circuits that operate at clock speeds up to 200 MHz, ” said Robert Bielby, director of strategic applications at Xilinx. “Customers benefit from these powerful features when implementing mathematical intensive functions such as DSP. The result is high performance and greater flexibility at a fraction of the cost.” Pricing and Availability
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-30- *Based upon volume projections of 250,000 units for the XC2S15 device.
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