SAN JOSE, Calif., September 25, 2000—Xilinx, Inc. (NASDAQ: XLNX) announced today the immediate availability of POS-PHY^TM Level 3 Link Layer and Physical Layer cores to address increasing internet protocol traffic demands by providing solutions for emerging Packet Over SONET (POS-PHY) applications for Xilinx® FPGAs. Both cores are compatible with POS-PHY Level 3 interface specified by the SATURN® Development Group. Xilinx is also developing the next-generation of POS-PHY Level 4 cores to provide OC-192 10 Gbps data transfer to accelerate the introduction of terabit routers and high-speed optical switches.

"PMC-Sierra's broad family of integrated POS-PHY Level 3 compatible framers coupled with the Xilinx FPGAs using POS-PHY Level 3 cores provide complementary solutions to our mutual customers," said Steve Perna, vice president and general manager of PMC-Sierra's Optical Networking Division. "With these solutions, broadband system designers can now rapidly develop highly functional, scalable and standards-based equipment to increase the speed of networks up to 2.5 Gb/sec to meet the exploding growth of IP traffic over SONET/SDH backbones."

Xilinx has also been active in the Optical Internetworking Forum (OIF) and the ATM Forum to drive POS-PHY Level 4 acceptance. Xilinx is the only FPGA company to demonstrate over 800 Mbps operation, confirming full speed capability to support the 10 Gbps OC-192 draft standard at the OIF (OIF2000.088.2). 

"The improved efficiencies of Packet-over-SONET/SDH (POS) is an enabling technology for gigabit routers, terabit and optical cross connect switches, and a wide range of SONET/SDH transmission systems," said Mark Aaldering, senior director for the IP Solutions Division at Xilinx.  "The POS-PHY cores and high-performance FPGAs from Xilinx allow next-generation network developers to reduce their system time-to-market." 

The Xilinx POS-PHY Level 3 cores are available for purchase as Xilinx LogiCORE^TM products, downloadable from the Xilinx IP Center, and optimized for Xilinx devices and design tools.  The cores are designed to operate with the latest Virtex FPGAs. The cores were developed in cooperation with ModelWare, Inc. a developer of virtual components for Telecommunications functions.

License price and availability 

The POS-PHY Level 3 Link layer and Physical Layer cores are available now. Pricing for the cores are $9,995 each. The POS-PHY Level 4 Link and Physical Layer cores will be available Q1 2001.  Licensing information and instructions for downloading the cores and information on all Xilinx LogiCORE products can be found at the Xilinx IP Center.

About Xilinx

Xilinx is the leading innovator of complete programmable logic solutions, including advanced integrated circuits, software design tools, predefined system functions delivered as cores, and unparalleled field engineering support. Founded in 1984 and headquartered in San Jose, Calif., Xilinx invented the field programmable gate array (FPGA) and fulfills more than half of the world demand for these devices today. Xilinx solutions enable customers to reduce significantly the time required to develop products for the computer, peripheral, telecommunications, networking, industrial control, instrumentation, high-reliability/military, and consumer markets. For more information, visit the Xilinx web site at www.xilinx.com.