SAN JOSE, Calif., April 19, 2000—Xilinx, Inc. (NASDAQ: XLNX) announced today a joint development effort with Synopsys, Inc. (NASDAQ:SNPS) to create a new incremental methodology for FPGA design. This methodology combines exclusive technology from Synopsys for Block Level Incremental Synthesis (BLIS) integrated with the Xilinx® guided place and route tools. This technology, a part of the Synopsys FPGA Express software version 3.4, will be available exclusively to Xilinx customers for nine months in the next version of the Xilinx Foundation Series^TM software release. BLIS is also available in the Synopsys FPGA Compiler II software for the Xilinx Virtex^TM FPGAs.

"Synopsys and Xilinx have teamed to provide this incremental synthesis technology," said Jay Michlin, Synopsys vice president and general manager of the FPGA business unit. "This is a groundbreaking incremental synthesis technology which enables the designer to quickly implement late arriving design changes, without having to re-synthesize the entire design, and potentially save weeks of design re-work."

In a separate announcement, Synopsys announced Block Level Incremental Synthesis, a methodology for making incremental design changes for late arriving functional or performance-related changes. Designers using high-density Xilinx Virtex FPGAs can now fully leverage Block Level Incremental Synthesis in the Foundation Series place and route software. 

"With the increase in the FPGA densities and intense time to market pressure, often design implementation and verification are performed in parallel resulting in design changes late in the design cycle," said Rich Sevcik, Xilinx senior vice president of service, IP solutions, and software. "This new methodology enables late stage design modifications while maintaining the timing for the remaining portion of the design."

Design modifications in complex designs may be necessary prior to final design handoff. BLIS delivers the ability to modify and re-optimize a designated block of logic in a previously routed design by producing separate netlists for each modified block. A key feature of BLIS is that it automatically recalculates the timing across the entire design, including the unmodified portions, while maintaining the timing of those unchanged portions. This provides predictability and stability when making incremental design changes late in the cycle. When targeting the high-density Virtex devices, BLIS greatly reduces iterations.

The new netlist is then implemented using the Xilinx guided implementation feature. Guided implementation uses a previously placed-and-routed FPGA as the blueprint for the next place-and-route iteration of the same design. This process is similar to the ASIC engineering change order (ECO) methodology in which the current place-and-route information is used for all parts of the design that have not changed. Guided implementation only addresses the changed portion of the design to ensure that the timing is identical for the unchanged portion.

License price and availability

Block Level Incremental Synthesis technology is available now directly from Synopsys and will be integrated into the next generation of Xilinx Foundation Series software due this quarter and starts at $1995.

Xilinx is the leading innovator of complete programmable logic solutions, including advanced integrated circuits, software design tools, predefined system functions delivered as cores, and unparalleled field engineering support. Founded in 1984 and headquartered in San Jose, Calif., Xilinx invented the field programmable gate array (FPGA) and fulfills more than half of the world demand for these devices today. Xilinx solutions enable customers to reduce significantly the time required to develop products for the computer, peripheral, telecommunications, networking, industrial control, instrumentation, high-reliability/military, and consumer markets. For more information, visit the Xilinx web site at www.xilinx.com.

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