| FOR IMMEDIATE RELEASE
XILINX DELIVERS TWO MILLION GATE VIRTEXÔ SOLUTION FOR GIGABIT PER SECOND APPLICATIONS Virtex-E family supports multiple 10 Gbit/sec ports and 266 MHz Double Data Rate memory performance
Also available: Virtex-E FAQ and Technical
Backgrounder
SAN JOSE, Calif., September 27, 1999—Less than a year after announcing the industry's first million-gate Virtex FPGA, XilinxÒ , Inc., (NASDAQ:XLNX) today announced the delivery of the initial members of its next generation Virtex-E FPGA family. Four family members are available including the new XCV2000EÔ device, with two million system gates, supporting twice the system-gate density and 50 percent higher I/O performance of the original Virtex FPGAs. The Virtex–E family will consist of 11 members, from 50,000 system gates to 3.2 million system gates within the second quarter next year. The new Virtex-E FPGAs, delivering new performance and density attributes that were only previously addressed by ASIC solutions, are ideally suited for future data communications and DSP applications. "The industry's demand for the Virtex series has been phenomenal and we expect that, with the enhancements we've made to the Virtex architecture, the Virtex-E family will set another precedent for excellence," said Wim Roelandts, Xilinx president and CEO. "The Virtex devices are already proving to our customers the time-saving advantages that these FPGAs bring to their design cycle. The density and performance levels, combined with the popular system-level features and industry-leading FPGA price points make Virtex-E FPGAs an even more compelling alternative to ASICs." "The Virtex series is the best of breed not just because of the advances in I/O technology and DLLs, but in gate density as well," said Paul Chang, manager of Hardware Design Group at Cisco Systems. "I'm very impressed with the Virtex SelectI/OÔ and DLL capabilities that enable us to manage both chip-to-chip interconnections within a single board, as well as board-to-board connections via the backplane. From an overall system design, the Virtex series allows us to get to market quickly without all the signal integrity issues at the board level. At Cisco, we're excited about the further enhancements in Virtex-E and look forward to using Virtex-E in our next generation systems." The Virtex-E family improves upon the FPGA standard that the original Virtex series has set: multiple I/O standards support, clock signal synchronization, and multiple memory resources. Users can reduce their overall design complexity, component count, and total system cost by utilizing the system integration features on Virtex devices. The Virtex-E family has made significant improvements in the areas of capacity and performance: 3.2 million gates (220 percent increase); 832 Kbits of True Dual-PortÔ internal blockRAM (650 percent increase); eight digital delay locked loops (DLLs) capable of over 300 MHz clock frequency for system timing (100 percent increase); and three new differential signal standards. The Virtex-E FPGAs are the first programmable logic devices delivered on 0.18-micron process technology, which Xilinx jointly produced with Taiwan's UMC Group. The improved process directly contributes to the 30 percent performance gain for all internal functionality. Also, the Virtex-E family represents the industry's first programmable logic architecture with 210 million transistors on a single device. The Virtex series has brought programmable logic to the core of leading-edge systems; two critical enablers in this are bandwidth and memory performance. Highest bandwidth and most flexible differential signal support Building on the highly flexible SelectI/O technology, Virtex-E is the first programmable device to support direct interface to multiple differential signal standards, including LVPECL, LVDS, and Bus LVDS (BLVDS). The Virtex-E family offers a hierarchy of differential solutions, including up to 36 I/O pairs for LVDS and LVPECL operating at 622 Mbits per second and up to 344 I/O pairs of LVDS, BLVDS, and LVPECL operating at 311 Mbits per second (providing an aggregate I/O bandwidth of over 100 Gbits per second). System designers can now leverage the high bandwidth and noise immunity solutions of the new SelectI/O+Ô technology, making Virtex-E the ideal solution for designing data communication systems with high signal integrity. Multiple 10 Gbits/sec ports in an FPGA The Virtex-E SelectI/O+ technology can support up to 804 user–selectable I/O pins with performance exceeding 311 Mbits per second per pin. The technology also supports up to 20 single-ended and differential signal standards. Delivering both performance and flexibility, the Virtex-E devices can now support a system application of multiple ports running over 10 Gbits per second— previously attainable only with an ASIC solution. 266 MHz DDR memory performance With further improvements in the SelectRAM+Ô capability, the Virtex-E family has significantly increased the amount of internal True Dual-Port memory resources bringing the total block memory support to 832 Kbits of RAM—almost twice the memory resources available on any other programmable logic family. In addition, the Virtex-E family provides up to one Mbits of internal distributed RAM, ideal for high-speed data processing systems where a small amount of wide memory is needed. Also, by using the SelectI/O+ and DLL capabilities, the Virtex-E device provides direct connections to high performance memory devices like the 266 MHz double data rate (DDR) SDRAM and 200 MHz Zero Bus TurnaroundÒ (ZBTÒ ) SRAM memory. "The performance of the Virtex architecture allows our customers to take full advantage of the bandwidth improvements realized with our new 200 MHz ZBT SRAM products, " said Charley Clark, vice president of IDT's SRAM Division. "The Virtex-E family will also be able to support the next generation Quad Data RateÔ (QDRÔ ) technologies which target future switches and routers that operate at data rates above 200 MHz. Our close relationship with Xilinx ensures that our customers will have continued early access to our highest performance memory solutions." QDR SRAMs and Quad Data Rate and Quad Data Rate comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology. Complete high performance design tools and intellectual property support The currently available version 2.1i Xilinx software, which continues the trend of 50 percent compile times reductions, provides support for up to two million gate designs. Support for densities beyond this will be in the next software release, available early next year. All the Xilinx Alliance SeriesÔ partners, including Exemplar, Synopsys, and Synplicity, now support the new Virtex-E architecture. With high-performance I/O operating at over 311 MHz, system designers can further enhance the signal integrity and noise immunity of their design via the EDA partners’ design tools. Through close collaboration with the Xilinx EDA partners combined with support for IBIS models, the following signal analysis tools can be used: XTK from Viewlogic, Interconnectix from Mentor Graphics, HyperLynx, and PCB Signal Analyzer from Veribest. These tools detect and analyze occurrences of overshoot/undershoot, impedance mismatches and crosstalk, which can impact system integrity of high performance systems. The Xilinx Smart-IPÔ technology now supports the new family. The CORE GeneratorÔ 2.1i tool supports Virtex-E series now. The popular BaseBLOXÔ cores and reference designs for Virtex-E are available in the IP CenterÔ site. The Real–PCI 64/66Ô , and the 32/33 Xilinx LogiCOREÔ PCI solutions are also available for the Virtex-E family. Consultants in the Xilinx XPERTsÔ partners program have been trained to support the Virtex-E series in design implementation and system level integration. Additional Xilinx DSP cores for architecture independent DSP solutions and cores from the 30 AllianceCOREÔ partners will be available for Virtex-E family later this year. Pricing, Packaging, and Availability All the benefits of Virtex technology continue for the Virtex-E series and enable industry-leading price points due to the Xilinx product development leadership based on the industry's most advanced processes. Projected high volume pricing starts at $16.50 for the XCV100EÔ devices with 100,000 system gates *. These enhanced Virtex-E features are available at price points that are projected to be lower than the Virtex family by mid-2000. The first members of the Virtex-E family, the XCV300EÔ , XCV600EÔ , XCV1000EÔ , and XCV2000EÔ devices, are available now. Standard packaging technologies for the Virtex-E family will be the same as those available for the Virtex family, including plastic quad flat packs, (PQFP), ball grid arrays (BGA), 1.0-mm fine pitch BGAs (FG), and 0.8-mm chip scale packages (CSP). Xilinx has added three new fine pitch BGA packages for the Virtex-E offering in 860- (FG860), 900- (FG900), and 1156-(FG1156) pin options. Xilinx is the leading innovator of complete programmable logic solutions, including advanced integrated circuits, software design tools, predefined system functions delivered as cores, and unparalleled field engineering support. Founded in 1984 and headquartered in San Jose, Calif., Xilinx invented the field programmable gate array (FPGA) and fulfills more than half of the world demand for these devices today. Xilinx solutions enable customers to significantly reduce the time required to develop products for the computer, peripheral, telecommunications, networking, industrial control, instrumentation, high-reliability/military, and consumer markets. For more information, visit the Xilinx web site at www.xilinx.com. ZBT and Zero Bus Turnaround are registered trademarks
of IDT Inc., and the architecture is supported by Micron Technology, Inc.
and Motorola Inc. QDR SRAMs and Quad Data Rate comprise a new family of
products developed by Cypress Semiconductor, IDT, and Micron Technology.
|