Q. What is the Virtex-E Extended Memory family?
The Virtex-E Extended Memory (Virtex-EM) is a 0.18 µm 1.8V FPGA family of two devices based on the Virtex-E architecture. The Virtex-EM family has the same features of the Virtex-E family architecture and includes additional block memory. This family is the first to deliver over 1M bits of block RAM, and is also the first FPGA to deploy copper interconnect.

Q. What applications require such extreme amounts of memory?
This family deploys a larger amount of block RAM for the equivalent logic gates as other FPGAs because it is targeted to support specific network and graphics applications that today either use external RAM, or use an ASIC that integrates a large amount of memory. The Virtex-EM family provides a combination of block RAM and logic that is geared to support applications such as 160 Gbps network switches (for the XCV812E^TM device) and for video imaging and graphics (for the XCV405E^TM device). 

Q. What are the differences between the Virtex-E family and the Virtex-EM family?
Both products are 0.18 micron, six-layer metal 1.8V family FPGAs. The differences are that the Virtex-EM deploys copper interconnect on the top two layers to optimize performance and power distribution, and minimize clock skew and signal skew. The architectures of the two families are the same, except for the block RAM increases described above.

Q. Where do the performance improvements come from?
The Virtex-EM family achieves higher memory bandwidth from increased on-chip memory, which reduces the performance lag associated with accessing external memory. Additional performance improvements come from the copper interconnect, which minimizes power supply drop throughout the device. The lower resistance copper interconnect used to route clock lines minimizes clock skew, once again leading to performance improvements. 

Q. Why did Xilinx increase the amount of RAM for this family?
There are two types of RAM in the Virtex-E FPGAs - distributed RAM, and block RAM. For the two Virtex-EM devices, we increased the amount of block RAM to support applications that typically use external memory for buffers. By integrating the block RAM on board the chip, we provide a single-chip solution for many applications. Designers do not need to use I/O to access external memory, plus there is no performance degradation caused by external memory accesses.

Q. What are some of the new markets and applications that Virtex-EM family will enable for Xilinx?
The Virtex-EM will have a good fit for next-generation network switch fabrics, including 160 Gbps crossbar switches. The family is also suited for video imaging applications that need to buffer eight or more video lines. In those applications, designers can integrate the buffer memory on the Virtex-EM, increasing integration of the solution.

Q. Have any customers demonstrated interest in this more RAM-intensive FPGA?
We have several customers who have found this product solves the unique challenges presented by their applications. In addition, customers who historically have used ASIC products to implement system functionality see that the programmable Virtex-EM can fit their applications with greater design flexibility and faster time to market than the ASIC alternative.

Q. Is this combination of logic and memory unique to the programmable logic industry?
The Virtex-EM family offers the first FPGA with more than one million bits of block RAM. Xilinx offers this product for memory-intensive applications that don’t require as many logic gates that are available in the largest Virtex-E devices. That is what makes the ratio of block RAM to logic in the Virtex-EM unique in the industry.

Q. Is Virtex-EM footprint compatible with the other Virtex families?
The Virtex-EM family is footprint compatible with Virtex-E products.

Q. Is Virtex-EM bitstream compatible with the other Virtex families?
The Virtex-EM family is not bitstream compatible with Virtex-E family products.

Q. Is there a price premium for Virtex-EM over Virtex or Virtex-E?
The Virtex-EM devices offer more than three times the block RAM of equivalent densities of a Virtex-E device. The family is priced to support new applications, and is priced close to the next higher density Virtex-E device.

Q. Does the Virtex-EM family support applications for reconfigurable computing? Is it partially reconfigurable?
Virtex-EM devices do support reconfigurable computing. Each device can be reconfigured to provide different functions at different times. A specific high-speed configuration port allows bitstreams to be downloaded into Virtex-EM devices at a rate up to 400 Mbit/second, which allows even the largest device to be completely reconfigured in milliseconds. Virtex-EM devices will also provide for partial reconfiguration, meaning a portion of the device can be changed while the rest of the device continues to operate. 

Q. Do Virtex-EM devices have the capability to support Internet Reconfigurable Logic (IRL)? 
The Virtex-EM devices, with their capability of supporting partial reconfiguration, are used as the hardware vehicle for implementing Xilinx Online^TM applications. 

Q. What is the system gate count for these Virtex-EM devices?
Using the gate-counting method that is consistent with previous Virtex and Spartan generation families, one may calculate the system gates for the XCV405E device as roughly 1.3 million system gates and for the XCV812E as roughly 3.1 million system gates. This is because the Virtex-EM family has a much larger block RAM to logic gate ratio. Still, system gate count comparisons between the Virtex-E and Virtex-EM families becomes less meaningful because of the employment of the RAM in a networking or high-definition video imaging designs. We've provided the number of logic gates plus the number of block RAM bits to allow system designers to chose the appropriate device for their application.

Q. When will software support be available for the Virtex-EM family?
The current Xilinx Alliance Series^TM and Foundation Series^TM  software, version 2.1i, fully support the XCV812E device. Software support for the XCV405E device will be available in Q2 2000. In addition, design-entry tools are available from leading third-party EDA vendors. 

Q. What IP Solutions are available for Virtex-EM FPGA? 
In the Xilinx tradition of having cores available at the time of silicon availability, the Virtex-EM family is supported with the latest release of cores currently available and downloadable from the IP center. All the cores can be installed for use via the Xilinx COREGenerator^TM System. This cores release includes many Smart IP^TM cores that are paratermizable, optimized, and predictable. For example, the release includes parameterizable generators for asynchronous FIFOs, block memory modules, distributed memory, parallel multipliers, FIR filters, FFTs, NCOs, Sine/Cosine LUT, and many more base level functions. The popular configurable Reed Solomon Encoder and Decoder cores are also available for this new family.

Q. What are the available packages?
Both Virtex-EM devices are available in the BG560 SBGA package. In addition, the devices are offered in Xilinx FinePitch (1.0-mm pitch) packages—the XCV405E device in the FinePitch FG676 and the XCV812E in the FG900.

Q. Will other densities be added to this family?
These devices were designed to support RAM intensive applications. For those applications that require even more RAM than the XCV405E device, Xilinx offers both the XCV812E device and higher density Virtex-E devices, such as the XCV2000E, XCV2600E, and XCV3200E devices. Future products from Xilinx will support applications requiring even higher RAM content than the XCV812E device.
 

			XCV405E	XCV812E
CLB Rows			40	56
CLB Columns			60	84
Logic Cells			10,800	21,168
Logic Gates			129,600	254,016
Block RAM (K bits)			560	1,120
Distributed RAM (K bits)			153	301
Max I/O			404	556
Differential I/O Pairs			183	201
Speed Grades			-6, -7, -8	-6, -7, -8
DLLs			8	8
Pkg	I/O	Size	ES Schedule	ES Schedule
BG560	404	42.5 x 42.5
FG676	444	27x27
FG900	700	31x31