Cadence Interface - Tips and Techniques

Concept-HDL

• Answer 1728 - How to generate a board-level symbol?
• Answer 2005 - How to integrate CORE Generator modules?

NC-Verilog

• Answer 947 - How to back annotate the SDF file for timing simulation?
• Answer 2554 - How to compile the 2.1i Verilog libraries?
• Answer 5474 - Running simulation?

Verilog-XL

• Answer 1089 - Specifying multiple libraries in a Verilog simulation?
• Answer 3767 - How to have NGD2VER automatically specify the addition of the `uselib directive and path to the SIMPRIMS library?
• Answer 6701 - Running simulation?