Virtex Configuration FAQ
The purpose of this FAQ is to answer questions about Virtex configuration.
This FAQ must be used together with the configuration switching characteristics
in the current Virtex Datasheet(V1.1). An application note on Virtex configuration
is now available XAPP138.
Q1: When is the non-JTAG configuration mode of the Virtex chip determined?
A1: The non-JTAG configuration mode for a Virtex device is determined
after Vccint reaches its minimum voltage and /INIT has gone high. When
the /INIT pin has gone high, the values on the mode pins, M2,M1, &
M0 are examined.
Q2: What configuration modes are possible with Virtex?
A2: There are 4 configuration modes in Virtex: slave serial, master
serial, SelectMAP, and JTAG.
Q3: What are the mode pin settings for the various non-JTAG configuration
modes in Virtex?
A3: Virtex Configuration Mode:M2M1M0
Slave serial: 111
Master serial: 000
SelectMAP: 110
JTAG: 101
Q4: Is it possible to make JTAG the only way to configure a Virtex
device?
A4: It is possible to enable only JTAG as the only way to configure
a Virtex device. By setting the mode pins M2, M1, and M0 to 101, the user
will only be able to configure the Virtex part via JTAG.
Q5: What pins are used to monitor the status of non-JTAG Virtex configuration?
A5: The two pins DONE and INIT can be used for observing the status
of non-JTAG Virtex configuration. During Virtex configuration, if the bitstream
has not been loaded, then the DONE pin is low. When the bitstream has been
loaded into the Virtex device the DONE pin goes high. The INIT pin is stays
high during configuration. If an error is detected while loading the configuration
bitstream, the INIT pin will drop low and the Virtex device will no longer
respond to input stimulus. During configuration the DOUT pin will not transition.
The DOUT pin remains disabled and pulled high during configuration, unless
configuration data needs to be sent to a Daisy-Chained device. After configuration
all unused IOs, including DOUT and INIT if unused in design, are disabled
but not pulled up. Unused IOs will float Low during normal operation.
Q6: What is the state of unconfigured IOB's in a Virtex device during
configuration?
A6: During Virtex configuration, unconfigured IOB's are tristated without
a pullup or pulldown.
Q7: After a Virtex device is configured, what is the state of unused
IOB's?
A7: After a Virtex device is configured, unused IOB's are configured
as a tristated OBUFT with a weak pulldown.
Q8: In a daisy-chain configuration, what configuration modes can
be used with a Virtex device?
A8: master serial, slave serial.
Q9: Can SelectMAP be used if a Virtex device needs to be configured
in a daisy-chain?
A9: No.
Q10: In a daisy-chain configuration with non-Virtex devices, what
position must the Virtex device occupy in the daisy-chain?
A10: Virtex FPGAs may only be daisy-chained with XC4000X (EX/XL/XV)
and SpartanXL and other Virtex FPGAs. There are no restrictions on the
order of the devices. However, grouping the devices by type will slightly
reduce the bitstream length (by no more than 100 bytes).
Q11:What is the default configuration mode for Virtex?
A11: If the mode pins on a Virtex device are left unconnected, the default
configuration mode is slave serial.
Q12: During a JTAG configuration of a Virtex device, how is the status
of the DONE and /INIT signals checked?
A12: In Virtex JTAG configuration, the status of the DONE and /INIT
signals can be observed by loading their values into the Virtex JTAG instruction
register. During JTAG configuration of a Virtex device, the status of the
DONE and /INIT pins can be observed by performing a CAPTURE- IR and shifting
out 4-bits from the instruction register. The first bit shifted out of
the instruction register will be a 1. The second bit shifted out will be
a 0. The third bit shifted out is the status of the DONE signal. The fourth
bit shifted out is the status of the /INIT signal.
Q13: Can the TAP pins of a Virtex device be used as regular I/O?
A13: The TAP pins of a Virtex device are fully dedicated boundary scan
pins. They cannot be used as regular I/O.
Q14: What is the relationship between CCLK and the DOUT when a Virtex
device is configuring?
A14: Data appears on the DOUT pin on the rising edge of CCLK. Note that
this is different from non-Virtex devices. In non-Virtex devices, data
appears on the DOUT pin on the falling edge of CCLK.
Q15: Is the Virtex serial configuration mode similar to the XC4000
serial configuration mode?
A15: The Virtex serial configuration mode is very similar to the XC4000
serial configuration mode. The main difference between the Virtex serial
configuration mode and XC4000 serial configuration mode is the number of
status pins. The Virtex device does not have an /LDC pin or HDC pin.
Q16: How do you change the CCLK rate of a Virtex device in master
serial configuration mode?
A16: The CCLK can be varied from 2.5 Mhz to 60 Mhz. The default master
serial configuration CCLK speed in Virtex master serial configuration is
2.5 Mhz. The bitgen program is used to change the CCLK frequency in Virtex
Master Serial Configuration mode.
Q17: How do you create an ASCII version of the Virtex bitstream that
can be used for configuring a Virtex device via SelectMAP with a microprocessor?
A17: The M1 software tool promgen can create an ASCII version of a Virtex
bitstream. Use the following command-line to create the ASCII bitstream
file: promgen -b -p hex -u 0 bitfile_name Where bitfile_name is a Virtex
bit file created by bitgen. The promgen options specified will create an
ASCII file that can be partitioned in the following manner:
D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7....
where D0, D1, D2,....D7 correspond to the D0, D1,D2,....D7 pins used
in SelectMAP configuration.
For related information, please refer to Answer
7112.
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