9500 Family Implementation Tools: Tips and Techniques
Design Entry Tools
Hardware/Programming Solutions
Core Implementation Tools
Power Sequencing/Estimation
Pin-Locking
Timing
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Design Entry Tools
Solution 1045: Foundation Simulator: XC9500 flip-flop outputs unknown (PRLD signal)
Solution 1651: XC9500: Configuring device I/Os as an open-drain (open-collector)
Solution 1706: XABEL: How to get Test Vectors (.TMV file) into an XC9500 JEDEC file.
Solution 3000: CPLD: XC9500/XL: Why do the XC9500/XL libraries have pull-up elements?
Solution 3123: XC9500/XL: How are initial states of flip-flops determined on 9500 CPLDs?
Solution 3705: Foundation-Express: XC9500 Recommended Synthesis and Fitter Options
Hints, Tips and Tricks for using XABEL with Xilinx M1.5 Design and Implementation Tools
A CPLD VHDL Introduction
Using ABEL with Xilinx CPLDs
Core Implementation Tools
Solution 983: XC9500/XL: How to set FAST slew rate for 9K outputs in PLUSASM and ABEL
Solution 1536: XC9500/XL: How are unused I/O pins handled?
Solution 2109: XC9500/XL: Fitter Report Equation Syntax
Solution 2579: XC9500: How to utilize the Wired-AND (WAND) in the UIM
Solution 2704: XC9500/XL: How does CPLD Auto Device Selection Work
Solution 2729: XC9500/XL: How to Control Logic Optimization in a CPLD
Solution 2860: XC9500/XL: How to read the CPLD report (.RPT) file?
Solution 3122: XC9500/XL: How do the BUFGSR, BUFG, and OE buffers work on the 9500/XL?
Solution 3194: XC9500/XL: What is the polarity for the tri-state enable for CPLDs?
Planning for High Speed XC9500XL Designs
Designing with XC9500XL CPLDs
Designing with XC9500 CPLDs
Pin-Locking
Solution 2719: CPLD: 9500/XL How to lock the pins on a CPLD
Pin Preassigning with XC9500 CPLDs
Hardware/Programming Solutions
Solution 2150: XC9500: The high level output voltage of an 9500 CPLD is ~4 volts
Solution 3026: XC9500/XL: When can I use internal pull-up resistors?
Solution 6717: How can I drive 5 volts from a 3.3-volt part?
Solution 3226: What are the recommended maximum rise times for inputs?
Solution 1308: XC9500: How many outputs can you simultaneously drive at 24 mA?
Solution 1490: XC9500: Device Slew Rates (Rise/Fall times) with capacitive loads
Solution 1536: XC9500/XL: How are unused I/O pins handled?
Solution 1603: XC9500/XL: When can the XC9500 internal IOB pullups be accessed?
Solution 1707: XC9500: Minimum Reset Signal Pulse Width.
Solution 2875: XC9500: Maximum Icc by package type
Solution 3116: Typical I/V Characteristics of XC9500 Outputs
Power Sequencing/Estimation
Solution 2717: XC9500/XL: How to control power consumption in a CPLD
Solution 2146: XC9500: How to place a macrocell/signal in low power mode (LOWPWR) in a CPLD
Solution 2653: Power estimation in 9500/XL family devices
XC9500 CPLD Power Sequencing
Understanding XC9500XL CPLD Power
Timing
Solution 2732: 9500/XL: How to control Timing Paths in a CPLD
Solution 3006: CPLD: How to calculate the timing across a latch in a 9K device
Solution 3302: CPLD: What are negative setup times in CPLD Performance report?
Using the XC9500 Timing Model
Using the XC9500XL Timing Model
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