Xilinx Foundation ISE: Top Solutions  To access our full database of Xilinx Solutions, please consult our Answers Search.   Foundation ISE and Synplicity 6.1 Integration Solution 10739 - 3.3.06i Foundation ISE, Project Navigator, Synplify - Where is the documentation regarding the Synplify Integration Solution 10486 - 3.3.06i Foundation ISE, Synplify - Remote sources will not work in the Synplify flows. Solution 10445 - 3.3.06i Foundation ISE, Project Navigator, Synplify - Synthesis "Process Properties" Help file is for XST. Solution 10446 - 3.3.06i Foundation ISE, Project Navigator, Synplify - Synthesis "Frequency" option is ignored. Solution 10444 - 3.3.06i Foundation ISE, Project Navigator, Synplify - Synplify errors are not displayed in the Project Navigator Console. Solution 10450 - 3.3.06i Foundation ISE, Project Navigator, Synplify - Schematic sources not supported in the Synplicity flows. Solution 10456 - 3.3.06i Foundation ISE, Project Navigator, Synplify - Node-locked licenses for Synplify not supported Solution 10452 - 3.3.06i Foundation ISE, Project Navigator, Synplify - Checkmarks not updated after running a design in Synplify GUI. Hot Solutions Solution 9273 - Foundation ISE 3.1i: Back-annotated Pin locations Process fails with exit code: 0002. Solution 9290 - Foundation ISE 3.1i: File -> Save As copies the project source files but does not copy the CoreGEN implementation and project files. This will result in Ngdbuild unexpanded block errors. Solution 9291 - Foundation ISE 3.1i: When the "Simulate Post Route HDL Model" is run, ngdanno and ngd2vhdl or ngd2ver is run to create a timing simulation netlist. The output of ngdanno is not written to the console window. Solution 9134 - Foundation ISE 3.1i: When source files containing functions are added to the project a red ? is displayed next to the function name. The red ? indicates that Project Navigator can not find a matching entity or module declaration Solution 9317 - Foundation ISE 3.1i: If the Implement Design process is run and synthesis fails a red checkmark is placed on Implement Design and not synthesis. This applies for ngdbuild and map also. Solution 9318 - Foundation ISE 3.1i: Checkmarks on the top level module are not properly updated when lower level module is changed. Solution 9260 - Foundation ISE 3.1i: Running the "Edit UCF File" process can result in the following error: cannot open C:\\path\\file.ucf This is caused when a user created UCF file is specified in the Translate Options. This is a CPLD only issue. Solution 9108 - Foundation ISE 3.1i: Users are required to specify a font each time a report or file is printed from the Report Viewer. Currently all Foundation ISE reports are opened in the Report Viewer Solution 9124 - Foundation ISE 3.1i: The 'Delete Implementation Data' menu pick does not delete the FPGA Express files or directory. Solution 9131 - Foundation ISE 3.1i: The VHDL language is compile order dependent, so users who want to have packages utilized by entities must consider the following. Solution 9095 - Foundation ISE 3.1i: Source files containing multiple pairs of entity/architecture definitions are not correctly displayed. Only the last entity/architecture in the file is displayed in Module view. Solution 9135 - Foundation ISE 3.1i: When deleting source files, a dialog is displayed with the following question, "Remove Selected File?" and two buttons "Yes" and "No". However, the file selected in the source window is not the file originally selected to be deleted. The problem is once the delete key is hit or the remove menu pick is selected, the cursor is moved to the next file. Solution 9133 - Foundation ISE 3.1i: When a source file from another directory is added to a project and synthesis fails, users will see inconsistent error reporting An example error message: ERROR : (VHP__0337). File D:\xst\cust_designs\trw\.\design\ctap.vhd. Line 623. Double clicking on the error, usually opens the file and places the cursor on the offending line. In this situation the file is opened but the cursor goes to the first line. Solution 9259 - Foundation ISE 3.1i: When the "Create Schematic Symbol" process is run on a Verilog Module, the component names are generated as lower-case names. This can result in synthesis errors because the associated components will not be found. CORE Generator specific issues Solution 9292 - Foundation ISE 3.1i: CoreGEN modules created in the Foundation ISE environment, which has module names longer than 11 characters will cause a Dr. Watson error in Foundation. Solution 9263 - Foundation ISE 3.1i: After a CORE has been created Project Navigator creates an ECS symbol and adds the XCO file to the project. However this does not happen if the options in Core Generator are opened. Solution 9264 - Foundation ISE 3.1i: After a CORE has been created Project Navigator creates an ECS symbol and adds the XCO file to the project. This does not happen fixed point cores. (FFT, 12x12 Multiplier, 8x8 Mult). Solution 9265 - Foundation ISE 3.1i: After a CORE has been created Project Navigator creates an ECS symbol, adds the XCO file to the project, and adds an instantiation template for the Core in the Language Templates. On Windows98 the template is missing everything but the comments.