to view the 
PDF files below. You can also
download
the entire xcell31.pdf file from our File Download site.
If you would like a subscription to the Xcell journal, use the literature
request form. If you have comments, suggestions, or would like
your design featured in Xcell, e-mail editor@xilinx.com.
In this Q1 '99 issue...
New Technology
Imagination
Springs to Life...
The
New Virtex FPGA Family - Much More Than Just a Million Gates
New
Internet Reconfigurable Logic for Creating Web-enabled Devices
Applications
Reed-Solomon
Cores Excel in the Virtex Architecture
Creating
Efficient Multi-Tap Shift Registers in Virtex LUTs
Designing
with Large, Fast Programmable Logic Devices
Efficient
Multi-Channel Serial to Parallel Converter
New
ASIC Estimator For Cost Modeling
See also: ASIC
Estimator
FPGA-Link
- System Level Integration of FPGAs
New
Virtex Card Provides FPGA-based Real Time Processing
Hierarchy
Management in Synplify
Anna-Liz:
A New Core for Debugging PCI Designs
New
CardBus and PCMCIA Cores for Xilinx FPGAs
Concept
HDL - New Standard
Success Stories
Using
the Xilinx Verilog Flow for Efficient High Speed Design
A
PCI Acquisition Board Using the XC4013
Product Information
CPLD
Fitter Shootout: Xilinx 1.5 versus Altera 9.01
XC9500XL
CPLDs Immune to Power Sequencing Problems
Frequency
Synthesis Techniques
JTAG
Boundary Scan for Low Cost System Testing
Hints & Issues
HDL
Advisor - Creating the Most Efficient Comparators
Hotline
Q&A: Virtex
Virtex
I/V Curves for Various Output Options
News Briefs
1
GHz Performance Milestone - 0.18m, 1.8V FPGA
Trade
Show Programs
See also: Trade Shows
Technical
Support - support.xilinx.com |
