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Virtex-II Handbook
 
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PDF File
About This Handbook 138KB
Introduction to the Virtex-II FPGA Family 105KB
Part 1: Virtex-II Data Sheet  
  Virtex-II Data Sheet  
Part 2: Virtex-II User Guide (version 1.3):
(Entire User Guide)
 15.93MB
  Chapter 1: Timing Models 421KB
  Chapter 2: Design Considerations (includes chapter subsections below) 2.67MB
    Using Global Clock Networks 265KB
    Using Digital Clock Manager (DCM) 1.17MB
    Using Block SelectRAMTM Memory 225KB
    Using Distributed SelectRAM Memory 166KB
    Using Shift Register Look-Up Tables 151KB
    Designing Large Multiplexers 155KB
    Designing Sum of Products (SOP) 116KB
    Using Embedded Multipliers 168KB
    Using Single-Ended SelectI/O Resources 368KB
    Using Digital Controlled Impedance (DCI) 202KB
    Using DDR I/O 158KB
    Using LVDS I/O 139KB
    Using Bitstream Encryption 123KB
    Using the CORE Generator System 428KB
  Download all VHDL Templates and Sub-Modules
89KB 
(zip file) 
Download all Verilog Templates and Sub-Modules
72KB 
(zip file) 
Chapter 3: Configuration 673KB
  Chapter 4: PCB Design Considerations (includes subsections below) 10.14MB
    Pinout Information 147KB
    Pinout Diagrams 1.31MB
    Package Specifications 746KB
    Flip-Chip Packages 746KB
    Thermal Data 85KB
    Printed Circuit Board Considerations 162KB
    Board Routability Guidelines 7.88MB
    Power Consumption 140KB
    IBIS Models 111KB
IBIS Files (web site)  
    BSDL and Boundary Scan Models 66KB
BSDL Files (web site)  
  Appendix A: Application Notes (summaries only) 125KB
    XAPP252: SigmaRAM DDR SRAM Interface for Virtex-II Devices*  
    XAPP253: DDR SDRAM Controller for Virtex-II Devices*  
    XAPP254: SiberCAM Interface for Virtex-II Devices  
    XAPP256: FIFOs Using Virtex-II Shift Registers  
    XAPP257: Asynchronous FIFO in Virtex-II Devices*  
    XAPP258: FIFOs Using Virtex-II Block RAM  
    XAPP260: Using Block RAM for High Performance Read/Write CAMs*  
    XAPP261: Data-Width Conversion FIFOs Using Virtex-II Block RAM Memory  
    XAPP262: QDR SRAM Interface for Virtex-II Devices*  
    XAPP266: FCRAM Controller for Virtex-II Devices*  
    XAPP267: Parity Generation and Validation in Virtex-II Devices  
    XAPP268: Dynamic Clock Data Alignment*  
    XAPP269: Fast CAM in Virtex-II Devices*  
  Appendix B: BitGen and PROMGen Switches and Options 280KB
  Appendix C: XC18V00 Series PROMs  
    PROM Package Specifications 229KB
    XC18V00 Series PROM Data Sheet 245KB
  Appendix D: Glossary 293KB

* - Full Application Notes coming soon. Abstracts of these items are available now.
Virtex-II Platform FPGAs
Data Sheets
Application Notes
Reference Designs
Tech Topics
IP Solutions
Virtex-II Endorsements
PCI-X
Xtreme DSP
Power Estimator Tool
Chipscope ILA Tool
SelectLink Tool
WebACE Tool