The Quarterly Journal for 
Xilinx Programmable Logic Users
Xcell 29 - Third Quarter, 1998

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In this Q3 '98 issue...

Products

Customer Success Stories

Development System

Special Section on Verification Verification for Higher Productivity Using Synopsys SmartModel FPGA Models to Verify Xilinx FPGA Designs Mixed Schematic and HDL Design Entry Verifying PCI Designs Viewlogic's Mixed-Design Verification Methodology The Basic Elements of HDL Simulation for FPGAs and CPLDs Board Design and Simulation Using OrCAD Express Post-Route Timing Analysis with Leonardo Spectrum Verification Using a Self-Checking Test Bench

HDL Verification:  We Will Take You to The Leaders

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