library "XC9500XL-parts" { fpga_library_version : "v1.0.0"; fpga_default_part : "XC9500XL"; fpga_part_library : 1; dm_library_is_internal : 1; design "XC9500XL" { read_only : 1; fpga_valid_speed_grades : [" "]; } design "9536XLPC44" { read_only : 1; fpga_valid_speed_grades : ["-5" "-7" "-10"]; } design "9536XLVQ44" { read_only : 1; fpga_valid_speed_grades : ["-5" "-7" "-10"]; } design "9536XLCS48" { read_only : 1; fpga_valid_speed_grades : ["-5" "-7" "-10"]; } design "9536XLVQ64" { read_only : 1; fpga_valid_speed_grades : ["-5" "-7" "-10"]; } design "9572XLPC44" { read_only : 1; fpga_valid_speed_grades : ["-5" "-7" "-10"]; } design "9572XLCS48" { read_only : 1; fpga_valid_speed_grades : ["-5" "-7" "-10"]; } design "9572XLVQ44" { read_only : 1; fpga_valid_speed_grades : ["-5" "-7" "-10"]; } design "9572XLVQ64" { read_only : 1; fpga_valid_speed_grades : ["-5" "-7" "-10"]; } design "9572XLTQ100" { read_only : 1; fpga_valid_speed_grades : ["-5" "-7" "-10"]; } design "95144XLTQ100" { read_only : 1; fpga_valid_speed_grades : ["-5" "-7" "-10"]; bmap_max_count_array : ["BUFGTS" "4"]; } design "95144XLCS144" { read_only : 1; fpga_valid_speed_grades : ["-5" "-7" "-10"]; bmap_max_count_array : ["BUFGTS" "4"]; } design "95144XLTQ144" { read_only : 1; fpga_valid_speed_grades : ["-5" "-7" "-10"]; bmap_max_count_array : ["BUFGTS" "4"]; } design "95288XLTQ144" { read_only : 1; fpga_valid_speed_grades : ["-6" "-7" "-10"]; bmap_max_count_array : ["BUFGTS" "4"]; } design "95288XLPQ208" { read_only : 1; fpga_valid_speed_grades : ["-6" "-7" "-10"]; bmap_max_count_array : ["BUFGTS" "4"]; } design "95288XLBG256" { read_only : 1; fpga_valid_speed_grades : ["-6" "-7" "-10"]; bmap_max_count_array : ["BUFGTS" "4"]; } design "95288XLFG256" { read_only : 1; fpga_valid_speed_grades : ["-6" "-7" "-10"]; bmap_max_count_array : ["BUFGTS" "4"]; } design "95288XLCS280" { read_only : 1; fpga_valid_speed_grades : ["-6" "-7" "-10"]; bmap_max_count_array : ["BUFGTS" "4"]; } }