Xilinx Answer #2649 : SYNPLIFY: How to change the bus-notation using syn_edif_bit_format and syn_edif_scalar

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SYNPLIFY: How to change the bus-notation using syn_edif_bit_format and syn_edif_scalar_format attributes?

Record #2649
Product Family: Software

Product Line: Synplicity

Product Part: Synplify

Product Version: 5.0

Problem Title:
SYNPLIFY: How to change the bus-notation using syn_edif_bit_format and
syn_edif_scalar_format attributes?

Problem Description:
Urgency: Standard

General Description:
How to change the bus-notation using syn_edif_bit_format
and syn_edif_scalar_format attributes?

There are several commonly used conventions for delimiting busses in netlists such as EDIF. Mixing conventions can cause problems with your design flow, so Synplicity has added additional user control to allow easier conformance to your chosen convention. Synplicity now provides you with the ability to control the formatting of EDIF netlists for use with Xilinx FPGAs.

As of Synplify 5.1.4 and later releases, you can specify the bus
format and the case of nets in the Xilinx EDIF netlist. The 2 new
attributes, syn_edif_bit_format and syn_edif_scalar_format, allow
you to specify the format either directly in the HDL code or by
applying the attribute preferences graphically in Synplify's
constraints editor (SCOPE).

The syn_edif_bit_format attribute is applied to the top level and
all black box modules/components in a design, syn_edif_bit_format
can be specified for vectors and takes the following values:

"%C<%i>" : Use <> to delimit bits of a bus

"%C[%i]" : Use [ ] to delimit bits of a bus

"%C(%i)" : Use ( ) to delimit bits of a bus

"%C_%i": Use _ to delimit bits of a bus [implies syn_noarray_ports=1]

"%C%i": Append bit to the name of a bus [implies syn_noarray_ports = 1]

See (Xilinx Solution 504) regarding the syn_noarray_ports attribute

The value of C can be:
u : to upshift the case of the base name of a bus
d : to downshift the case of the base name of a bus
n : to preserve the case of the base name of a bus

For example, given a bus definition: My_Bus[1:0]

%n<%i> should rename My_Bus to
           My_Bus<1:0>

%u(%i) should rename My_Bus to
           MY_BUS(1:0)

%d[%i] should rename My_Bus to
           my_bus[1:0]

%n_%i should rename My_Bus to
           My_Bus_1
           My_Bus_0

%u%i should rename My_Bus to
           MY_BUS1
           MY_BUS0

Solution 1:

Verilog
------

Apply on a module basis

module d_register (CLK, D_IN, Q_OUT)
   /* synthesis syn_edif_bit_format="%u<%i>" */;
input CLK;
input [3:0] D_IN;
output [3:0] Q_OUT;

reg [3:0] Q_OUT;

always @ (posedge CLK)
   Q_OUT <= D_IN;

endmodule

Solution 2:

VHDL
----

Apply on an architecture/component basis

Component example:

component test
     port ( ? );
end component;
attribute syn_edif_bit_format : string;
attribute syn_edif_scalar_format : string;
attribute syn_edif_bit_format of test : component is "%u(%i)";
attribute syn_edif_scalar_format of test : component is "%u";

Architecture example:

architecture XILINX of test is
attribute syn_edif_bit_format : string;
attribute syn_edif_scalar_format : string;
attribute syn_edif_bit_format of XILINX : architecture is "%u(%i)";
attribute syn_edif_scalar_format of XILINX : architecture is "%u";

Solution 3:

SDC
---

# syn_edif_bit_format attribute
define_global_attribute syn_edif_bit_format {%n[%i]}

# syn_edif_scalar_format attribute
define_global_attribute syn_edif_scalar_format {%n}

Please note that %u and %d can be substituted for
%n for upshifting and downshifting of the base name.

End of Record #2649 - Last Modified: 06/08/99 15:37

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