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SYNPLIFY: How to selectively disable IBUF/OBUF insertion using .ispad or black_box_pad_pin?
Record #4508
Problem Title:
SYNPLIFY: How to selectively disable IBUF/OBUF insertion using .ispad or black_box_pad_pin?
Problem Description:
Urgency: Standard
General Description: How to selectively disable IBUF/OBUF
insertion?
Synplify will automatically insert an IBUF/OBUF on all signals
listed in the port list of the top level module/entity of the
design. If a user includes a pre-optimized netlist that contains
I/O cells (like IBUF, OBUF, OFD, etc.), then these ports must be
marked to disable this feature.
Define the module/entity that contains embedded I/O cells as a
black_box. Then for these ports, attach an attribute called
.ispad (5.0.6 or earlier) or black_box_pad_pin (5.0.7 and later)
which declares the ports as pads, and hence Synplify does not
insert buffers for them.
In Synplify 5.0.7 and later, the black_box_pad_pin attribute is
introduced. This is recognized for all Xilinx families. However,
the .ispad attribute is recognized for all Xilinx families except
Virtex.
Solution 1:
-- VHDL (selective I/O insertion)
-- Using black_box_pad_pin attribute
-- Used with Synplify 5.0.7 and later
-- The black_box_pad_pin is recognized for all families.
-- Define a black box component. It is not necessary to
-- to instantiate a black box entity and architecture.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FOO1 is
port(A, B : in std_logic_vector(3 downto 0);
C : out std_logic_vector(3 downto 0);
WE : out std_logic);
end FOO1;
architecture BEHAVE of FOO1 is
begin
C <= A + B;
WE <= A(0) and A(1) and A(2) and A(3);
end BEHAVE;
library ieee, synplify;
use ieee.std_logic_1164.all;
use synplify.attributes.all; -- Define Synplify attributes
entity TOP is
port (A, B1, B2 : in std_logic_vector(3 downto 0);
C, D : out std_logic_vector(3 downto 0);
ACTIVE : out std_logic);
end TOP;
architecture BEAVE of top is
component FOO1
port(A, B : in std_logic_vector(3 downto 0);
C : out std_logic_vector(3 downto 0);
WE : out std_logic);
end component;
component FOO2
port(A, B : in std_logic_vector(3 downto 0);
WE : in std_logic;
D : out std_logic_vector(3 downto 0);
ACT : out std_logic);
end component;
attribute black_box of FOO2 : component is true;
attribute black_box_pad_pin of FOO2 : component is "D(3:0), ACT";
signal WE : std_logic;
begin
U0 : FOO1 port map (A => A, B => B1, C => C, WE => WE);
U1 : FOO2 port map (A => A, B => B2, WE => WE, D => D, ACT => ACTIVE);
end BEAVE;
Solution 2:
// Verilog (selective I/O insertion)
// Using the .ispad attribute
// Used with Synplify 5.0.6 and earliar
// The .ispad is recognized for all families except Virtex
module FOO1 (A, B, C, WE);
input [3:0] A, B;
output [3:0] C;
output WE;
assign C = A + B;
assign WE = A[0] & A[1] & A[2] & A[3];
endmodule
// The .ispad is applied to the ports of the module that
// is declared as a black_box.
module FOO2 (A, B, WE, D, ACT) /* synthesis black_box */;
input [3:0] A, B;
input WE;
output [3:0] D /* synthesis .ispad = 1 */;
output ACT /* synthesis .ispad = 1 */;
endmodule
module TOP (A, B1, B2, C, D, ACTIVE);
input [3:0] A, B1, B2;
output [3:0] C, D;
output ACTIVE;
wire WE;
FOO1 U0 (.A (A), .B (B1), .C (C), .WE (WE));
FOO2 U1 (.A (A), .B (B2), .WE (WE), .D (D), .ACT (ACTIVE));
endmodule
Solution 3:
-- VHDL (selective I/O insertion)
-- Using the .ispad attribute
-- Used with Synplify 5.0.6 and earliar
-- The .ispad is recognized for all families except Virtex
-- Define a black box entity and architecture for the model
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FOO1 is
port(A, B : in std_logic_vector(3 downto 0);
C : out std_logic_vector(3 downto 0);
WE : out std_logic);
end FOO1;
architecture BEHAVE of FOO1 is
begin
C <= A + B;
WE <= A(0) and A(1) and A(2) and A(3);
end BEHAVE;
library ieee;
use ieee.std_logic_1164.all;
entity FOO2 is
port(A, B : in std_logic_vector(3 downto 0);
WE : in std_logic;
D : out std_logic_vector(3 downto 0);
ACT : out std_logic);
-- The .ispad attribute is applied to the ports of the entity
-- that is declared as a black box.
attribute \.ispad\ : boolean;
attribute \.ispad\ of D : signal is true;
attribute \.ispad\ of ACT : signal is true;
end FOO2;
architecture BEHAVE of foo2 is
attribute black_box : boolean;
attribute black_box of BEHAVE : architecture is true;
begin
end BEHAVE;
library ieee;
use ieee.std_logic_1164.all;
entity TOP is
port (A, B1, B2 : in std_logic_vector(3 downto 0);
C, D : out std_logic_vector(3 downto 0);
ACTIVE : out std_logic);
end TOP;
architecture BEAVE of top is
component FOO1
port(A, B : in std_logic_vector(3 downto 0);
C : out std_logic_vector(3 downto 0);
WE : out std_logic);
end component;
component FOO2
port(A, B : in std_logic_vector(3 downto 0);
WE : in std_logic;
D : out std_logic_vector(3 downto 0);
ACT : out std_logic);
end component;
signal WE : std_logic;
begin
U0 : FOO1 port map (A => A, B => B1, C => C, WE => WE);
U1 : FOO2 port map (A => A, B => B2, WE => WE, D => D, ACT => ACTIVE);
end BEAVE;
Solution 4:
// Using black_box_pad_pin attribute
// Used with Synplify 5.0.7 and later
// The black_box_pad_pin is recognized for all families
module FOO1 (A, B, C, WE);
input [3:0] A, B;
output [3:0] C;
output WE;
assign C = A + B;
assign WE = A[0] & A[1] & A[2] & A[3];
endmodule
module FOO2 (A, B, WE, D, ACT)
/* synthesis black_box black_box_pad_pin="D[3:0],ACT" */;
input [3:0] A, B;
input WE;
output [3:0] D;
output ACT;
endmodule
module TOP (A, B1, B2, C, D, ACTIVE);
input [3:0] A, B1, B2;
output [3:0] C, D;
output ACTIVE;
wire WE;
FOO1 U0 (.A (A), .B (B1), .C (C), .WE (WE));
FOO2 U1 (.A (A), .B (B2), .WE (WE), .D (D), .ACT (ACTIVE));
endmodule
End of Record #4508 - Last Modified: 07/08/99 10:08 |
